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From: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
To: qemu-devel@nongnu.org
Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk,
	kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com,
	palmer@dabbelt.com, alistair.francis@wdc.com,
	bin.meng@windriver.com, pbonzini@redhat.com,
	philipp.tomsich@vrull.eu, kvm@vger.kernel.org,
	qemu-riscv@nongnu.org, richard.henderson@linaro.org
Subject: [PATCH v3 02/19] target/riscv: Refactor vector-vector translation macro
Date: Fri, 28 Apr 2023 15:47:40 +0100	[thread overview]
Message-ID: <20230428144757.57530-3-lawrence.hunter@codethink.co.uk> (raw)
In-Reply-To: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk>

From: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>

Refactor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into
function `opivv_trans` (similar to `opivi_trans`). `opivv_trans` will be
used in proceeding vector-crypto commits.

Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@codethink.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 62 +++++++++++++------------
 1 file changed, 32 insertions(+), 30 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index f2e3d385152..4106bd69949 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1643,38 +1643,40 @@ GEN_OPIWX_WIDEN_TRANS(vwadd_wx)
 GEN_OPIWX_WIDEN_TRANS(vwsubu_wx)
 GEN_OPIWX_WIDEN_TRANS(vwsub_wx)
 
+static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t vm,
+                        gen_helper_gvec_4_ptr *fn, DisasContext *s)
+{
+    uint32_t data = 0;
+    TCGLabel *over = gen_new_label();
+    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+    tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
+
+    data = FIELD_DP32(data, VDATA, VM, vm);
+    data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+    data = FIELD_DP32(data, VDATA, VTA, s->vta);
+    data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);
+    data = FIELD_DP32(data, VDATA, VMA, s->vma);
+    tcg_gen_gvec_4_ptr(vreg_ofs(s, vd), vreg_ofs(s, 0), vreg_ofs(s, vs1),
+                       vreg_ofs(s, vs2), cpu_env, s->cfg_ptr->vlen / 8,
+                       s->cfg_ptr->vlen / 8, data, fn);
+    mark_vs_dirty(s);
+    gen_set_label(over);
+    return true;
+}
+
 /* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */
 /* OPIVV without GVEC IR */
-#define GEN_OPIVV_TRANS(NAME, CHECK)                               \
-static bool trans_##NAME(DisasContext *s, arg_rmrr *a)             \
-{                                                                  \
-    if (CHECK(s, a)) {                                             \
-        uint32_t data = 0;                                         \
-        static gen_helper_gvec_4_ptr * const fns[4] = {            \
-            gen_helper_##NAME##_b, gen_helper_##NAME##_h,          \
-            gen_helper_##NAME##_w, gen_helper_##NAME##_d,          \
-        };                                                         \
-        TCGLabel *over = gen_new_label();                          \
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
-        tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
-                                                                   \
-        data = FIELD_DP32(data, VDATA, VM, a->vm);                 \
-        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);             \
-        data = FIELD_DP32(data, VDATA, VTA, s->vta);               \
-        data =                                                     \
-            FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\
-        data = FIELD_DP32(data, VDATA, VMA, s->vma);               \
-        tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),     \
-                           vreg_ofs(s, a->rs1),                    \
-                           vreg_ofs(s, a->rs2), cpu_env,           \
-                           s->cfg_ptr->vlen / 8,                   \
-                           s->cfg_ptr->vlen / 8, data,             \
-                           fns[s->sew]);                           \
-        mark_vs_dirty(s);                                          \
-        gen_set_label(over);                                       \
-        return true;                                               \
-    }                                                              \
-    return false;                                                  \
+#define GEN_OPIVV_TRANS(NAME, CHECK)                                     \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a)                   \
+{                                                                        \
+    if (CHECK(s, a)) {                                                   \
+        static gen_helper_gvec_4_ptr * const fns[4] = {                  \
+            gen_helper_##NAME##_b, gen_helper_##NAME##_h,                \
+            gen_helper_##NAME##_w, gen_helper_##NAME##_d,                \
+        };                                                               \
+        return opivv_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\
+    }                                                                    \
+    return false;                                                        \
 }
 
 /*
-- 
2.40.1



  parent reply	other threads:[~2023-04-28 14:49 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-28 14:47 [PATCH v3 00/19] Add RISC-V vector cryptographic instruction set support Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 01/19] target/riscv: Refactor some of the generic vector functionality Lawrence Hunter
2023-04-29  1:29   ` Weiwei Li
2023-04-28 14:47 ` Lawrence Hunter [this message]
2023-04-29  1:31   ` [PATCH v3 02/19] target/riscv: Refactor vector-vector translation macro Weiwei Li
2023-04-28 14:47 ` [PATCH v3 03/19] target/riscv: Remove redundant "cpu_vl == 0" checks Lawrence Hunter
2023-04-29  2:36   ` Weiwei Li
2023-04-28 14:47 ` [PATCH v3 04/19] target/riscv: Add Zvbc ISA extension support Lawrence Hunter
2023-04-29  2:58   ` Weiwei Li
2023-04-28 14:47 ` [PATCH v3 05/19] target/riscv: Move vector translation checks Lawrence Hunter
2023-04-29  3:04   ` Weiwei Li
2023-04-28 14:47 ` [PATCH v3 06/19] target/riscv: Refactor translation of vector-widening instruction Lawrence Hunter
2023-04-29  3:06   ` Weiwei Li
2023-04-28 14:47 ` [PATCH v3 07/19] target/riscv: Refactor some of the generic vector functionality Lawrence Hunter
2023-04-29  3:10   ` Weiwei Li
2023-04-28 14:47 ` [PATCH v3 08/19] qemu/bitops.h: Limit rotate amounts Lawrence Hunter
2023-05-01 19:56   ` Richard Henderson
2023-05-02 20:11   ` Richard Henderson
2023-04-28 14:47 ` [PATCH v3 09/19] tcg: Add andcs and rotrs tcg gvec ops Lawrence Hunter
2023-05-01 20:20   ` Richard Henderson
2023-04-28 14:47 ` [PATCH v3 10/19] qemu/host-utils.h: Add clz and ctz functions for lower-bit integers Lawrence Hunter
2023-05-01 19:56   ` Richard Henderson
2023-04-28 14:47 ` [PATCH v3 11/19] target/riscv: Add Zvbb ISA extension support Lawrence Hunter
2023-04-29  3:15   ` Weiwei Li
2023-04-28 14:47 ` [PATCH v3 12/19] target/riscv: Add Zvkned " Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 13/19] target/riscv: Add Zvknh " Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 14/19] target/riscv: Add Zvksh " Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 15/19] target/riscv: Add Zvkg " Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 16/19] crypto: Create sm4_subword Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 17/19] crypto: Add SM4 constant parameter CK Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 18/19] target/riscv: Add Zvksed ISA extension support Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 19/19] target/riscv: Expose Zvk* and Zvb[b, c] cpu properties Lawrence Hunter
2023-04-29  3:21   ` Weiwei Li
2023-06-16  9:21 ` [PATCH v3 00/19] Add RISC-V vector cryptographic instruction set support Daniel Henrique Barboza
2023-06-16 15:03   ` Max Chou

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