From: Lawrence Hunter <lawrence.hunter@codethink.co.uk>
To: qemu-devel@nongnu.org
Cc: dickon.hood@codethink.co.uk, nazar.kazakov@codethink.co.uk,
kiran.ostrolenk@codethink.co.uk, frank.chang@sifive.com,
palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, pbonzini@redhat.com,
philipp.tomsich@vrull.eu, kvm@vger.kernel.org,
qemu-riscv@nongnu.org, richard.henderson@linaro.org
Subject: [PATCH v3 05/19] target/riscv: Move vector translation checks
Date: Fri, 28 Apr 2023 15:47:43 +0100 [thread overview]
Message-ID: <20230428144757.57530-6-lawrence.hunter@codethink.co.uk> (raw)
In-Reply-To: <20230428144757.57530-1-lawrence.hunter@codethink.co.uk>
From: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Move the checks out of `do_opiv{v,x,i}_gvec{,_shift}` functions
and into the corresponding macros. This enables the functions to be
reused in proceeding commits without check duplication.
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvv.c.inc | 28 +++++++++++--------------
1 file changed, 12 insertions(+), 16 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 2660dda42be..21731b784ec 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1183,9 +1183,6 @@ do_opivv_gvec(DisasContext *s, arg_rmrr *a, GVecGen3Fn *gvec_fn,
gen_helper_gvec_4_ptr *fn)
{
TCGLabel *over = gen_new_label();
- if (!opivv_check(s, a)) {
- return false;
- }
tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
@@ -1218,6 +1215,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
}; \
+ if (!opivv_check(s, a)) { \
+ return false; \
+ } \
return do_opivv_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
}
@@ -1276,10 +1276,6 @@ static inline bool
do_opivx_gvec(DisasContext *s, arg_rmrr *a, GVecGen2sFn *gvec_fn,
gen_helper_opivx *fn)
{
- if (!opivx_check(s, a)) {
- return false;
- }
-
if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
TCGv_i64 src1 = tcg_temp_new_i64();
@@ -1301,6 +1297,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
}; \
+ if (!opivx_check(s, a)) { \
+ return false; \
+ } \
return do_opivx_gvec(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
}
@@ -1432,10 +1431,6 @@ static inline bool
do_opivi_gvec(DisasContext *s, arg_rmrr *a, GVecGen2iFn *gvec_fn,
gen_helper_opivx *fn, imm_mode_t imm_mode)
{
- if (!opivx_check(s, a)) {
- return false;
- }
-
if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
gvec_fn(s->sew, vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2),
extract_imm(s, a->rs1, imm_mode), MAXSZ(s), MAXSZ(s));
@@ -1453,6 +1448,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##OPIVX##_b, gen_helper_##OPIVX##_h, \
gen_helper_##OPIVX##_w, gen_helper_##OPIVX##_d, \
}; \
+ if (!opivx_check(s, a)) { \
+ return false; \
+ } \
return do_opivi_gvec(s, a, tcg_gen_gvec_##SUF, \
fns[s->sew], IMM_MODE); \
}
@@ -1775,10 +1773,6 @@ static inline bool
do_opivx_gvec_shift(DisasContext *s, arg_rmrr *a, GVecGen2sFn32 *gvec_fn,
gen_helper_opivx *fn)
{
- if (!opivx_check(s, a)) {
- return false;
- }
-
if (a->vm && s->vl_eq_vlmax && !(s->vta && s->lmul < 0)) {
TCGv_i32 src1 = tcg_temp_new_i32();
@@ -1800,7 +1794,9 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
gen_helper_##NAME##_b, gen_helper_##NAME##_h, \
gen_helper_##NAME##_w, gen_helper_##NAME##_d, \
}; \
- \
+ if (!opivx_check(s, a)) { \
+ return false; \
+ } \
return do_opivx_gvec_shift(s, a, tcg_gen_gvec_##SUF, fns[s->sew]); \
}
--
2.40.1
next prev parent reply other threads:[~2023-04-28 14:49 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-28 14:47 [PATCH v3 00/19] Add RISC-V vector cryptographic instruction set support Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 01/19] target/riscv: Refactor some of the generic vector functionality Lawrence Hunter
2023-04-29 1:29 ` Weiwei Li
2023-04-28 14:47 ` [PATCH v3 02/19] target/riscv: Refactor vector-vector translation macro Lawrence Hunter
2023-04-29 1:31 ` Weiwei Li
2023-04-28 14:47 ` [PATCH v3 03/19] target/riscv: Remove redundant "cpu_vl == 0" checks Lawrence Hunter
2023-04-29 2:36 ` Weiwei Li
2023-04-28 14:47 ` [PATCH v3 04/19] target/riscv: Add Zvbc ISA extension support Lawrence Hunter
2023-04-29 2:58 ` Weiwei Li
2023-04-28 14:47 ` Lawrence Hunter [this message]
2023-04-29 3:04 ` [PATCH v3 05/19] target/riscv: Move vector translation checks Weiwei Li
2023-04-28 14:47 ` [PATCH v3 06/19] target/riscv: Refactor translation of vector-widening instruction Lawrence Hunter
2023-04-29 3:06 ` Weiwei Li
2023-04-28 14:47 ` [PATCH v3 07/19] target/riscv: Refactor some of the generic vector functionality Lawrence Hunter
2023-04-29 3:10 ` Weiwei Li
2023-04-28 14:47 ` [PATCH v3 08/19] qemu/bitops.h: Limit rotate amounts Lawrence Hunter
2023-05-01 19:56 ` Richard Henderson
2023-05-02 20:11 ` Richard Henderson
2023-04-28 14:47 ` [PATCH v3 09/19] tcg: Add andcs and rotrs tcg gvec ops Lawrence Hunter
2023-05-01 20:20 ` Richard Henderson
2023-04-28 14:47 ` [PATCH v3 10/19] qemu/host-utils.h: Add clz and ctz functions for lower-bit integers Lawrence Hunter
2023-05-01 19:56 ` Richard Henderson
2023-04-28 14:47 ` [PATCH v3 11/19] target/riscv: Add Zvbb ISA extension support Lawrence Hunter
2023-04-29 3:15 ` Weiwei Li
2023-04-28 14:47 ` [PATCH v3 12/19] target/riscv: Add Zvkned " Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 13/19] target/riscv: Add Zvknh " Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 14/19] target/riscv: Add Zvksh " Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 15/19] target/riscv: Add Zvkg " Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 16/19] crypto: Create sm4_subword Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 17/19] crypto: Add SM4 constant parameter CK Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 18/19] target/riscv: Add Zvksed ISA extension support Lawrence Hunter
2023-04-28 14:47 ` [PATCH v3 19/19] target/riscv: Expose Zvk* and Zvb[b, c] cpu properties Lawrence Hunter
2023-04-29 3:21 ` Weiwei Li
2023-06-16 9:21 ` [PATCH v3 00/19] Add RISC-V vector cryptographic instruction set support Daniel Henrique Barboza
2023-06-16 15:03 ` Max Chou
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