From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Subject: [PULL 06/12] tcg: Add tcg_gen_gvec_rotrs
Date: Tue, 2 May 2023 12:20:17 +0100 [thread overview]
Message-ID: <20230502112023.776823-7-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230502112023.776823-1-richard.henderson@linaro.org>
From: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Add tcg expander and helper functions for rotate right
vector with scalar operand.
Signed-off-by: Nazar Kazakov <nazar.kazakov@codethink.co.uk>
Message-Id: <20230428144757.57530-10-lawrence.hunter@codethink.co.uk>
[rth: Split out of larger patch; mask rotation count.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-op-gvec.h | 2 ++
tcg/tcg-op-gvec.c | 11 +++++++++++
2 files changed, 13 insertions(+)
diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
index 6d58683171..a8183bfeab 100644
--- a/include/tcg/tcg-op-gvec.h
+++ b/include/tcg/tcg-op-gvec.h
@@ -371,6 +371,8 @@ void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs,
TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz);
void tcg_gen_gvec_rotls(unsigned vece, uint32_t dofs, uint32_t aofs,
TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_rotrs(unsigned vece, uint32_t dofs, uint32_t aofs,
+ TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz);
/*
* Perform vector shift by vector element, modulo the element size.
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 9c14908a46..f51bcaa87b 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -3353,6 +3353,17 @@ void tcg_gen_gvec_rotls(unsigned vece, uint32_t dofs, uint32_t aofs,
do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g);
}
+void tcg_gen_gvec_rotrs(unsigned vece, uint32_t dofs, uint32_t aofs,
+ TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz)
+{
+ TCGv_i32 tmp = tcg_temp_ebb_new_i32();
+
+ tcg_gen_neg_i32(tmp, shift);
+ tcg_gen_andi_i32(tmp, tmp, (8 << vece) - 1);
+ tcg_gen_gvec_rotls(vece, dofs, aofs, tmp, oprsz, maxsz);
+ tcg_temp_free_i32(tmp);
+}
+
/*
* Expand D = A << (B % element bits)
*
--
2.34.1
next prev parent reply other threads:[~2023-05-02 11:22 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-02 11:20 [PULL 00/12] tcg patch queue Richard Henderson
2023-05-02 11:20 ` [PULL 01/12] softmmu: Tidy dirtylimit_dirty_ring_full_time Richard Henderson
2023-05-02 11:20 ` [PULL 02/12] accel/tcg: Uncache the host address for instruction fetch when tlb size < 1 Richard Henderson
2023-05-02 11:20 ` [PULL 03/12] qemu/bitops.h: Limit rotate amounts Richard Henderson
2023-05-02 11:20 ` [PULL 04/12] qemu/host-utils.h: Add clz and ctz functions for lower-bit integers Richard Henderson
2023-05-02 11:20 ` [PULL 05/12] tcg: Add tcg_gen_gvec_andcs Richard Henderson
2023-05-02 11:20 ` Richard Henderson [this message]
2023-05-02 11:20 ` [PULL 07/12] qemu/int128: Re-shuffle Int128Alias members Richard Henderson
2023-05-02 11:20 ` [PULL 08/12] migration/xbzrle: Use __attribute__((target)) for avx512 Richard Henderson
2023-05-02 11:20 ` [PULL 09/12] accel/tcg: Add cpu_ld*_code_mmu Richard Henderson
2023-05-02 11:20 ` [PULL 10/12] tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64 Richard Henderson
2023-05-02 11:20 ` [PULL 11/12] tcg/mips: " Richard Henderson
2023-05-02 11:20 ` [PULL 12/12] tcg: Introduce tcg_out_movext2 Richard Henderson
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