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Tue, 02 May 2023 13:18:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PULL v2 00/12] tcg patch queue Date: Tue, 2 May 2023 21:18:17 +0100 Message-Id: <20230502201818.1726224-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The following changes since commit c586691e676214eb7edf6a468e84e7ce3b314d43: Merge tag 'pull-target-arm-20230502-2' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2023-05-02 16:38:29 +0100) are available in the Git repository at: https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230502-2 for you to fetch changes up to 129f1f9ee7df77d367d961b3c25353612d33cd83: tcg: Introduce tcg_out_movext2 (2023-05-02 13:05:45 -0700) ---------------------------------------------------------------- Misc tcg-related patch queue. v2: Update bitops.h rotate patch. ---------------------------------------------------------------- Dickon Hood (1): qemu/bitops.h: Limit rotate amounts Kiran Ostrolenk (1): qemu/host-utils.h: Add clz and ctz functions for lower-bit integers Nazar Kazakov (2): tcg: Add tcg_gen_gvec_andcs tcg: Add tcg_gen_gvec_rotrs Richard Henderson (7): softmmu: Tidy dirtylimit_dirty_ring_full_time qemu/int128: Re-shuffle Int128Alias members migration/xbzrle: Use __attribute__((target)) for avx512 accel/tcg: Add cpu_ld*_code_mmu tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64 tcg/mips: Conditionalize tcg_out_exts_i32_i64 tcg: Introduce tcg_out_movext2 Weiwei Li (1): accel/tcg: Uncache the host address for instruction fetch when tlb size < 1 meson.build | 5 +-- accel/tcg/tcg-runtime.h | 1 + include/exec/cpu_ldst.h | 9 ++++++ include/qemu/bitops.h | 16 +++++----- include/qemu/host-utils.h | 54 +++++++++++++++++++++++++++++++ include/qemu/int128.h | 4 +-- include/tcg/tcg-op-gvec.h | 4 +++ accel/tcg/cputlb.c | 53 ++++++++++++++++++++++++++++++ accel/tcg/tcg-runtime-gvec.c | 11 +++++++ accel/tcg/user-exec.c | 58 +++++++++++++++++++++++++++++++++ migration/xbzrle.c | 9 +++--- softmmu/dirtylimit.c | 15 ++++++--- tcg/tcg-op-gvec.c | 28 ++++++++++++++++ tcg/tcg.c | 69 +++++++++++++++++++++++++++++++++++++--- tcg/arm/tcg-target.c.inc | 44 +++++++++++-------------- tcg/i386/tcg-target.c.inc | 19 +++++------ tcg/loongarch64/tcg-target.c.inc | 4 ++- tcg/mips/tcg-target.c.inc | 4 ++- 18 files changed, 339 insertions(+), 68 deletions(-)