* [PULL v2 00/12] tcg patch queue
@ 2023-05-02 20:18 Richard Henderson
2023-05-02 20:18 ` [PULL v2 03/12] qemu/bitops.h: Limit rotate amounts Richard Henderson
2023-05-03 6:26 ` [PULL v2 00/12] tcg patch queue Richard Henderson
0 siblings, 2 replies; 4+ messages in thread
From: Richard Henderson @ 2023-05-02 20:18 UTC (permalink / raw)
To: qemu-devel
The following changes since commit c586691e676214eb7edf6a468e84e7ce3b314d43:
Merge tag 'pull-target-arm-20230502-2' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2023-05-02 16:38:29 +0100)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230502-2
for you to fetch changes up to 129f1f9ee7df77d367d961b3c25353612d33cd83:
tcg: Introduce tcg_out_movext2 (2023-05-02 13:05:45 -0700)
----------------------------------------------------------------
Misc tcg-related patch queue.
v2: Update bitops.h rotate patch.
----------------------------------------------------------------
Dickon Hood (1):
qemu/bitops.h: Limit rotate amounts
Kiran Ostrolenk (1):
qemu/host-utils.h: Add clz and ctz functions for lower-bit integers
Nazar Kazakov (2):
tcg: Add tcg_gen_gvec_andcs
tcg: Add tcg_gen_gvec_rotrs
Richard Henderson (7):
softmmu: Tidy dirtylimit_dirty_ring_full_time
qemu/int128: Re-shuffle Int128Alias members
migration/xbzrle: Use __attribute__((target)) for avx512
accel/tcg: Add cpu_ld*_code_mmu
tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64
tcg/mips: Conditionalize tcg_out_exts_i32_i64
tcg: Introduce tcg_out_movext2
Weiwei Li (1):
accel/tcg: Uncache the host address for instruction fetch when tlb size < 1
meson.build | 5 +--
accel/tcg/tcg-runtime.h | 1 +
include/exec/cpu_ldst.h | 9 ++++++
include/qemu/bitops.h | 16 +++++-----
include/qemu/host-utils.h | 54 +++++++++++++++++++++++++++++++
include/qemu/int128.h | 4 +--
include/tcg/tcg-op-gvec.h | 4 +++
accel/tcg/cputlb.c | 53 ++++++++++++++++++++++++++++++
accel/tcg/tcg-runtime-gvec.c | 11 +++++++
accel/tcg/user-exec.c | 58 +++++++++++++++++++++++++++++++++
migration/xbzrle.c | 9 +++---
softmmu/dirtylimit.c | 15 ++++++---
tcg/tcg-op-gvec.c | 28 ++++++++++++++++
tcg/tcg.c | 69 +++++++++++++++++++++++++++++++++++++---
tcg/arm/tcg-target.c.inc | 44 +++++++++++--------------
tcg/i386/tcg-target.c.inc | 19 +++++------
tcg/loongarch64/tcg-target.c.inc | 4 ++-
tcg/mips/tcg-target.c.inc | 4 ++-
18 files changed, 339 insertions(+), 68 deletions(-)
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PULL v2 03/12] qemu/bitops.h: Limit rotate amounts
2023-05-02 20:18 [PULL v2 00/12] tcg patch queue Richard Henderson
@ 2023-05-02 20:18 ` Richard Henderson
2023-05-03 6:26 ` [PULL v2 00/12] tcg patch queue Richard Henderson
1 sibling, 0 replies; 4+ messages in thread
From: Richard Henderson @ 2023-05-02 20:18 UTC (permalink / raw)
To: qemu-devel; +Cc: Dickon Hood
From: Dickon Hood <dickon.hood@codethink.co.uk>
Rotates have been fixed up to only allow for reasonable rotate amounts
(ie, no rotates >7 on an 8b value etc.) This fixes a problem with riscv
vector rotate instructions.
Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230428144757.57530-9-lawrence.hunter@codethink.co.uk>
[rth: Mask shifts in both directions.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/qemu/bitops.h | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index 03213ce952..cb3526d1f4 100644
--- a/include/qemu/bitops.h
+++ b/include/qemu/bitops.h
@@ -218,7 +218,7 @@ static inline unsigned long find_first_zero_bit(const unsigned long *addr,
*/
static inline uint8_t rol8(uint8_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((8 - shift) & 7));
+ return (word << (shift & 7)) | (word >> (-shift & 7));
}
/**
@@ -228,7 +228,7 @@ static inline uint8_t rol8(uint8_t word, unsigned int shift)
*/
static inline uint8_t ror8(uint8_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((8 - shift) & 7));
+ return (word >> (shift & 7)) | (word << (-shift & 7));
}
/**
@@ -238,7 +238,7 @@ static inline uint8_t ror8(uint8_t word, unsigned int shift)
*/
static inline uint16_t rol16(uint16_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((16 - shift) & 15));
+ return (word << (shift & 15)) | (word >> (-shift & 15));
}
/**
@@ -248,7 +248,7 @@ static inline uint16_t rol16(uint16_t word, unsigned int shift)
*/
static inline uint16_t ror16(uint16_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((16 - shift) & 15));
+ return (word >> (shift & 15)) | (word << (-shift & 15));
}
/**
@@ -258,7 +258,7 @@ static inline uint16_t ror16(uint16_t word, unsigned int shift)
*/
static inline uint32_t rol32(uint32_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((32 - shift) & 31));
+ return (word << (shift & 31)) | (word >> (-shift & 31));
}
/**
@@ -268,7 +268,7 @@ static inline uint32_t rol32(uint32_t word, unsigned int shift)
*/
static inline uint32_t ror32(uint32_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((32 - shift) & 31));
+ return (word >> (shift & 31)) | (word << (-shift & 31));
}
/**
@@ -278,7 +278,7 @@ static inline uint32_t ror32(uint32_t word, unsigned int shift)
*/
static inline uint64_t rol64(uint64_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((64 - shift) & 63));
+ return (word << (shift & 63)) | (word >> (-shift & 63));
}
/**
@@ -288,7 +288,7 @@ static inline uint64_t rol64(uint64_t word, unsigned int shift)
*/
static inline uint64_t ror64(uint64_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((64 - shift) & 63));
+ return (word >> (shift & 63)) | (word << (-shift & 63));
}
/**
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PULL v2 00/12] tcg patch queue
2023-05-02 20:18 [PULL v2 00/12] tcg patch queue Richard Henderson
2023-05-02 20:18 ` [PULL v2 03/12] qemu/bitops.h: Limit rotate amounts Richard Henderson
@ 2023-05-03 6:26 ` Richard Henderson
1 sibling, 0 replies; 4+ messages in thread
From: Richard Henderson @ 2023-05-03 6:26 UTC (permalink / raw)
To: qemu-devel
On 5/2/23 21:18, Richard Henderson wrote:
> The following changes since commit c586691e676214eb7edf6a468e84e7ce3b314d43:
>
> Merge tag 'pull-target-arm-20230502-2' ofhttps://git.linaro.org/people/pmaydell/qemu-arm into staging (2023-05-02 16:38:29 +0100)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230502-2
>
> for you to fetch changes up to 129f1f9ee7df77d367d961b3c25353612d33cd83:
>
> tcg: Introduce tcg_out_movext2 (2023-05-02 13:05:45 -0700)
>
> ----------------------------------------------------------------
> Misc tcg-related patch queue.
>
> v2: Update bitops.h rotate patch.
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/8.1 as appropriate.
r~
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PULL v2 03/12] qemu/bitops.h: Limit rotate amounts
2023-05-03 7:20 [PATCH 00/84] tcg: Build once for system, once for user Richard Henderson
@ 2023-05-03 7:20 ` Richard Henderson
0 siblings, 0 replies; 4+ messages in thread
From: Richard Henderson @ 2023-05-03 7:20 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, philmd, marcel.apfelbaum, wangyanan55, anjo, Dickon Hood
From: Dickon Hood <dickon.hood@codethink.co.uk>
Rotates have been fixed up to only allow for reasonable rotate amounts
(ie, no rotates >7 on an 8b value etc.) This fixes a problem with riscv
vector rotate instructions.
Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230428144757.57530-9-lawrence.hunter@codethink.co.uk>
[rth: Mask shifts in both directions.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/qemu/bitops.h | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index 03213ce952..cb3526d1f4 100644
--- a/include/qemu/bitops.h
+++ b/include/qemu/bitops.h
@@ -218,7 +218,7 @@ static inline unsigned long find_first_zero_bit(const unsigned long *addr,
*/
static inline uint8_t rol8(uint8_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((8 - shift) & 7));
+ return (word << (shift & 7)) | (word >> (-shift & 7));
}
/**
@@ -228,7 +228,7 @@ static inline uint8_t rol8(uint8_t word, unsigned int shift)
*/
static inline uint8_t ror8(uint8_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((8 - shift) & 7));
+ return (word >> (shift & 7)) | (word << (-shift & 7));
}
/**
@@ -238,7 +238,7 @@ static inline uint8_t ror8(uint8_t word, unsigned int shift)
*/
static inline uint16_t rol16(uint16_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((16 - shift) & 15));
+ return (word << (shift & 15)) | (word >> (-shift & 15));
}
/**
@@ -248,7 +248,7 @@ static inline uint16_t rol16(uint16_t word, unsigned int shift)
*/
static inline uint16_t ror16(uint16_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((16 - shift) & 15));
+ return (word >> (shift & 15)) | (word << (-shift & 15));
}
/**
@@ -258,7 +258,7 @@ static inline uint16_t ror16(uint16_t word, unsigned int shift)
*/
static inline uint32_t rol32(uint32_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((32 - shift) & 31));
+ return (word << (shift & 31)) | (word >> (-shift & 31));
}
/**
@@ -268,7 +268,7 @@ static inline uint32_t rol32(uint32_t word, unsigned int shift)
*/
static inline uint32_t ror32(uint32_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((32 - shift) & 31));
+ return (word >> (shift & 31)) | (word << (-shift & 31));
}
/**
@@ -278,7 +278,7 @@ static inline uint32_t ror32(uint32_t word, unsigned int shift)
*/
static inline uint64_t rol64(uint64_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((64 - shift) & 63));
+ return (word << (shift & 63)) | (word >> (-shift & 63));
}
/**
@@ -288,7 +288,7 @@ static inline uint64_t rol64(uint64_t word, unsigned int shift)
*/
static inline uint64_t ror64(uint64_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((64 - shift) & 63));
+ return (word >> (shift & 63)) | (word << (-shift & 63));
}
/**
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
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