* [PULL v2 00/12] tcg patch queue
@ 2023-05-02 20:18 Richard Henderson
2023-05-02 20:18 ` [PULL v2 03/12] qemu/bitops.h: Limit rotate amounts Richard Henderson
2023-05-03 6:26 ` [PULL v2 00/12] tcg patch queue Richard Henderson
0 siblings, 2 replies; 4+ messages in thread
From: Richard Henderson @ 2023-05-02 20:18 UTC (permalink / raw)
To: qemu-devel
The following changes since commit c586691e676214eb7edf6a468e84e7ce3b314d43:
Merge tag 'pull-target-arm-20230502-2' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2023-05-02 16:38:29 +0100)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230502-2
for you to fetch changes up to 129f1f9ee7df77d367d961b3c25353612d33cd83:
tcg: Introduce tcg_out_movext2 (2023-05-02 13:05:45 -0700)
----------------------------------------------------------------
Misc tcg-related patch queue.
v2: Update bitops.h rotate patch.
----------------------------------------------------------------
Dickon Hood (1):
qemu/bitops.h: Limit rotate amounts
Kiran Ostrolenk (1):
qemu/host-utils.h: Add clz and ctz functions for lower-bit integers
Nazar Kazakov (2):
tcg: Add tcg_gen_gvec_andcs
tcg: Add tcg_gen_gvec_rotrs
Richard Henderson (7):
softmmu: Tidy dirtylimit_dirty_ring_full_time
qemu/int128: Re-shuffle Int128Alias members
migration/xbzrle: Use __attribute__((target)) for avx512
accel/tcg: Add cpu_ld*_code_mmu
tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64
tcg/mips: Conditionalize tcg_out_exts_i32_i64
tcg: Introduce tcg_out_movext2
Weiwei Li (1):
accel/tcg: Uncache the host address for instruction fetch when tlb size < 1
meson.build | 5 +--
accel/tcg/tcg-runtime.h | 1 +
include/exec/cpu_ldst.h | 9 ++++++
include/qemu/bitops.h | 16 +++++-----
include/qemu/host-utils.h | 54 +++++++++++++++++++++++++++++++
include/qemu/int128.h | 4 +--
include/tcg/tcg-op-gvec.h | 4 +++
accel/tcg/cputlb.c | 53 ++++++++++++++++++++++++++++++
accel/tcg/tcg-runtime-gvec.c | 11 +++++++
accel/tcg/user-exec.c | 58 +++++++++++++++++++++++++++++++++
migration/xbzrle.c | 9 +++---
softmmu/dirtylimit.c | 15 ++++++---
tcg/tcg-op-gvec.c | 28 ++++++++++++++++
tcg/tcg.c | 69 +++++++++++++++++++++++++++++++++++++---
tcg/arm/tcg-target.c.inc | 44 +++++++++++--------------
tcg/i386/tcg-target.c.inc | 19 +++++------
tcg/loongarch64/tcg-target.c.inc | 4 ++-
tcg/mips/tcg-target.c.inc | 4 ++-
18 files changed, 339 insertions(+), 68 deletions(-)
^ permalink raw reply [flat|nested] 4+ messages in thread* [PULL v2 03/12] qemu/bitops.h: Limit rotate amounts
2023-05-02 20:18 [PULL v2 00/12] tcg patch queue Richard Henderson
@ 2023-05-02 20:18 ` Richard Henderson
2023-05-03 6:26 ` [PULL v2 00/12] tcg patch queue Richard Henderson
1 sibling, 0 replies; 4+ messages in thread
From: Richard Henderson @ 2023-05-02 20:18 UTC (permalink / raw)
To: qemu-devel; +Cc: Dickon Hood
From: Dickon Hood <dickon.hood@codethink.co.uk>
Rotates have been fixed up to only allow for reasonable rotate amounts
(ie, no rotates >7 on an 8b value etc.) This fixes a problem with riscv
vector rotate instructions.
Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230428144757.57530-9-lawrence.hunter@codethink.co.uk>
[rth: Mask shifts in both directions.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/qemu/bitops.h | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index 03213ce952..cb3526d1f4 100644
--- a/include/qemu/bitops.h
+++ b/include/qemu/bitops.h
@@ -218,7 +218,7 @@ static inline unsigned long find_first_zero_bit(const unsigned long *addr,
*/
static inline uint8_t rol8(uint8_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((8 - shift) & 7));
+ return (word << (shift & 7)) | (word >> (-shift & 7));
}
/**
@@ -228,7 +228,7 @@ static inline uint8_t rol8(uint8_t word, unsigned int shift)
*/
static inline uint8_t ror8(uint8_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((8 - shift) & 7));
+ return (word >> (shift & 7)) | (word << (-shift & 7));
}
/**
@@ -238,7 +238,7 @@ static inline uint8_t ror8(uint8_t word, unsigned int shift)
*/
static inline uint16_t rol16(uint16_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((16 - shift) & 15));
+ return (word << (shift & 15)) | (word >> (-shift & 15));
}
/**
@@ -248,7 +248,7 @@ static inline uint16_t rol16(uint16_t word, unsigned int shift)
*/
static inline uint16_t ror16(uint16_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((16 - shift) & 15));
+ return (word >> (shift & 15)) | (word << (-shift & 15));
}
/**
@@ -258,7 +258,7 @@ static inline uint16_t ror16(uint16_t word, unsigned int shift)
*/
static inline uint32_t rol32(uint32_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((32 - shift) & 31));
+ return (word << (shift & 31)) | (word >> (-shift & 31));
}
/**
@@ -268,7 +268,7 @@ static inline uint32_t rol32(uint32_t word, unsigned int shift)
*/
static inline uint32_t ror32(uint32_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((32 - shift) & 31));
+ return (word >> (shift & 31)) | (word << (-shift & 31));
}
/**
@@ -278,7 +278,7 @@ static inline uint32_t ror32(uint32_t word, unsigned int shift)
*/
static inline uint64_t rol64(uint64_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((64 - shift) & 63));
+ return (word << (shift & 63)) | (word >> (-shift & 63));
}
/**
@@ -288,7 +288,7 @@ static inline uint64_t rol64(uint64_t word, unsigned int shift)
*/
static inline uint64_t ror64(uint64_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((64 - shift) & 63));
+ return (word >> (shift & 63)) | (word << (-shift & 63));
}
/**
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PULL v2 00/12] tcg patch queue
2023-05-02 20:18 [PULL v2 00/12] tcg patch queue Richard Henderson
2023-05-02 20:18 ` [PULL v2 03/12] qemu/bitops.h: Limit rotate amounts Richard Henderson
@ 2023-05-03 6:26 ` Richard Henderson
1 sibling, 0 replies; 4+ messages in thread
From: Richard Henderson @ 2023-05-03 6:26 UTC (permalink / raw)
To: qemu-devel
On 5/2/23 21:18, Richard Henderson wrote:
> The following changes since commit c586691e676214eb7edf6a468e84e7ce3b314d43:
>
> Merge tag 'pull-target-arm-20230502-2' ofhttps://git.linaro.org/people/pmaydell/qemu-arm into staging (2023-05-02 16:38:29 +0100)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230502-2
>
> for you to fetch changes up to 129f1f9ee7df77d367d961b3c25353612d33cd83:
>
> tcg: Introduce tcg_out_movext2 (2023-05-02 13:05:45 -0700)
>
> ----------------------------------------------------------------
> Misc tcg-related patch queue.
>
> v2: Update bitops.h rotate patch.
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/8.1 as appropriate.
r~
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 00/84] tcg: Build once for system, once for user
@ 2023-05-03 7:20 Richard Henderson
2023-05-03 7:20 ` [PULL v2 03/12] qemu/bitops.h: Limit rotate amounts Richard Henderson
0 siblings, 1 reply; 4+ messages in thread
From: Richard Henderson @ 2023-05-03 7:20 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, philmd, marcel.apfelbaum, wangyanan55, anjo
Based-on: 20230503070656.1746170-1-richard.henderson@linaro.org
("[PATCH v4 00/57] tcg: Improve atomicity support")
and also
Based-on: 20230502160846.1289975-1-richard.henderson@linaro.org
("[PATCH 00/16] tcg: Remove TARGET_ALIGNED_ONLY")
The goal here is only tcg/, leaving accel/tcg/ for future work.
r~
Richard Henderson (84):
tcg: Split out memory ops to tcg-op-ldst.c
tcg: Widen gen_insn_data to uint64_t
accel/tcg: Widen tcg-ldst.h addresses to uint64_t
tcg: Widen helper_{ld,st}_i128 addresses to uint64_t
tcg: Widen helper_atomic_* addresses to uint64_t
tcg: Widen tcg_gen_code pc_start argument to uint64_t
accel/tcg: Merge gen_mem_wrapped with plugin_gen_empty_mem_callback
accel/tcg: Merge do_gen_mem_cb into caller
tcg: Reduce copies for plugin_gen_mem_callbacks
accel/tcg: Widen plugin_gen_empty_mem_callback to i64
tcg: Add addr_type to TCGContext
tcg: Remove TCGv from tcg_gen_qemu_{ld,st}_*
tcg: Remove TCGv from tcg_gen_atomic_*
tcg: Split INDEX_op_qemu_{ld,st}* for guest address size
tcg/tci: Elimnate TARGET_LONG_BITS, target_ulong
tcg/i386: Always enable TCG_TARGET_HAS_extr[lh]_i64_i32
tcg/i386: Conditionalize tcg_out_extu_i32_i64
tcg/i386: Adjust type of tlb_mask
tcg/i386: Remove TARGET_LONG_BITS, TCG_TYPE_TL
tcg/arm: Remove TARGET_LONG_BITS
tcg/aarch64: Remove USE_GUEST_BASE
tcg/aarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL
tcg/loongarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL
tcg/mips: Remove TARGET_LONG_BITS, TCG_TYPE_TL
tcg/ppc: Remove TARGET_LONG_BITS, TCG_TYPE_TL
tcg/riscv: Remove TARGET_LONG_BITS, TCG_TYPE_TL
tcg/s390x: Remove TARGET_LONG_BITS, TCG_TYPE_TL
tcg/sparc64: Remove TARGET_LONG_BITS, TCG_TYPE_TL
tcg: Remove TARGET_LONG_BITS, TCG_TYPE_TL
tcg: Move TCG_TYPE_TL from tcg.h to tcg-op.h
tcg: Add page_bits and page_mask to TCGContext
tcg: Add tlb_dyn_max_bits to TCGContext
tcg: Widen CPUTLBEntry comparators to 64-bits
tcg: Add tlb_fast_offset to TCGContext
tcg: Remove TCG_TARGET_TLB_DISPLACEMENT_BITS
tcg: Split out tcg/debug-assert.h
*: Add missing includes of qemu/error-report.h
*: Add missing includes of tcg/debug-assert.h
*: Add missing includes of tcg/tcg.h
tcg: Split out tcg-target-reg-bits.h
target/arm: Fix test of TCG_OVERSIZED_GUEST
tcg: Split out tcg/oversized-guest.h
tcg: Move TCGv, dup_const_tl definitions to tcg-op.h
tcg: Split tcg/tcg-op-common.h from tcg/tcg-op.h
target/arm: Include helper-gen.h in translator.h
target/hexagon: Include helper-gen.h where needed
tcg: Remove outdated comments in helper-head.h
tcg: Move TCGHelperInfo and dependencies to tcg/helper-info.h
tcg: Pass TCGHelperInfo to tcg_gen_callN
tcg: Move temp_idx and tcgv_i32_temp debug out of line
tcg: Split tcg_gen_callN
tcg: Split helper-gen.h
tcg: Split helper-proto.h
tcg: Add insn_start_words to TCGContext
tcg: Add guest_mo to TCGContext
tcg: Move TLB_FLAGS_MASK check out of get_alignment_bits
tcg: Split tcg/tcg-op-gvec.h
tcg: Remove NO_CPU_IO_DEFS
exec-all: Widen tb_page_addr_t for user-only
exec-all: Widen TranslationBlock pc and cs_base to 64-bits
tcg: Remove DEBUG_DISAS
tcg: Remove USE_TCG_OPTIMIZATIONS
tcg: Spit out exec/translation-block.h
include/exec: Remove CODE_GEN_AVG_BLOCK_SIZE
accel/tcg: Move most of gen-icount.h into translator.c
accel/tcg: Introduce translator_io_start
accel/tcg: Move translator_fake_ldb out of line
target/arm: Tidy helpers for translation
target/mips: Tidy helpers for translation
*: Add missing includes of exec/translation-block.h
*: Add missing includes of exec/exec-all.h
accel/tcg: Tidy includes for translator.[ch]
tcg: Define IN_TCG
tcg: Fix PAGE/PROT confusion
tcg: Move env defines out of NEED_CPU_H in helper-head.h
tcg: Remove target-specific headers from tcg.[ch]
plugins: Move plugin_insn_append to translator.c
plugins: Drop unused headers from exec/plugin-gen.h
disas: Move disas.c to disas/
disas: Remove target_ulong from the interface
tcg: Split out exec/user/guest-base.h
disas: Remove target-specific headers
exec/poison: Do not poison CONFIG_SOFTMMU
tcg: Build once for system and once for user-only
accel/tcg/tcg-runtime.h | 50 +-
include/disas/disas.h | 23 +-
include/exec/cpu-all.h | 8 +-
include/exec/cpu-defs.h | 50 +-
include/exec/cpu_ldst.h | 22 +-
include/exec/exec-all.h | 148 +-
include/exec/gen-icount.h | 83 --
include/exec/helper-gen-common.h | 17 +
include/exec/helper-gen.h | 96 +-
include/exec/helper-head.h | 24 +-
include/exec/helper-proto-common.h | 17 +
include/exec/helper-proto.h | 72 +-
include/exec/helper-tcg.h | 75 -
include/exec/plugin-gen.h | 28 +-
include/exec/poison.h | 1 -
include/exec/tlb-common.h | 56 +
include/exec/translation-block.h | 152 ++
include/exec/translator.h | 24 +-
include/exec/user/guest-base.h | 12 +
include/qemu/typedefs.h | 1 +
include/tcg/debug-assert.h | 17 +
include/tcg/helper-info.h | 64 +
include/tcg/insn-start-words.h | 17 +
include/tcg/oversized-guest.h | 23 +
include/tcg/tcg-ldst.h | 26 +-
include/tcg/tcg-op-common.h | 996 +++++++++++++
include/tcg/tcg-op-gvec-common.h | 426 ++++++
include/tcg/tcg-op-gvec.h | 444 +-----
include/tcg/tcg-op.h | 1118 ++-------------
include/tcg/tcg-opc.h | 41 +-
include/tcg/tcg.h | 153 +-
target/arm/tcg/translate.h | 5 +
target/mips/tcg/translate.h | 5 +-
target/ppc/cpu.h | 2 -
target/sparc/cpu.h | 2 -
tcg/aarch64/tcg-target-reg-bits.h | 12 +
tcg/aarch64/tcg-target.h | 1 -
tcg/arm/tcg-target-reg-bits.h | 12 +
tcg/arm/tcg-target.h | 1 -
tcg/i386/tcg-target-reg-bits.h | 16 +
tcg/i386/tcg-target.h | 9 +-
tcg/loongarch64/tcg-target-reg-bits.h | 21 +
tcg/loongarch64/tcg-target.h | 11 -
tcg/mips/tcg-target-reg-bits.h | 18 +
tcg/mips/tcg-target.h | 9 -
tcg/ppc/tcg-target-reg-bits.h | 16 +
tcg/ppc/tcg-target.h | 6 -
tcg/riscv/tcg-target-reg-bits.h | 19 +
tcg/riscv/tcg-target.h | 10 -
tcg/s390x/tcg-target-reg-bits.h | 17 +
tcg/s390x/tcg-target.h | 1 -
tcg/sparc64/tcg-target-reg-bits.h | 12 +
tcg/sparc64/tcg-target.h | 1 -
tcg/tcg-internal.h | 47 +-
tcg/tci/tcg-target-reg-bits.h | 18 +
tcg/tci/tcg-target.h | 9 -
accel/tcg/cpu-exec.c | 4 +-
accel/tcg/cputlb.c | 43 +-
accel/tcg/monitor.c | 1 +
accel/tcg/perf.c | 8 +-
accel/tcg/plugin-gen.c | 74 +-
accel/tcg/tcg-accel-ops-mttcg.c | 2 +-
accel/tcg/tcg-accel-ops-rr.c | 2 +-
accel/tcg/tcg-all.c | 1 +
accel/tcg/tcg-runtime-gvec.c | 2 +-
accel/tcg/tcg-runtime.c | 6 +-
accel/tcg/translate-all.c | 58 +-
accel/tcg/translator.c | 142 +-
accel/tcg/user-exec.c | 31 +-
disas.c => disas/disas.c | 22 +-
linux-user/elfload.c | 5 +-
target/alpha/translate.c | 18 +-
target/arm/ptw.c | 8 +-
target/arm/tcg/translate-a64.c | 38 +-
target/arm/tcg/translate-m-nocp.c | 2 -
target/arm/tcg/translate-mve.c | 4 -
target/arm/tcg/translate-neon.c | 4 -
target/arm/tcg/translate-sme.c | 7 -
target/arm/tcg/translate-sve.c | 11 -
target/arm/tcg/translate-vfp.c | 7 +-
target/arm/tcg/translate.c | 41 +-
target/avr/cpu.c | 1 +
target/avr/helper.c | 1 +
target/avr/translate.c | 6 +-
target/cris/translate.c | 8 +-
target/hexagon/genptr.c | 1 +
target/hexagon/translate.c | 7 +
target/hppa/translate.c | 10 +-
target/i386/helper.c | 3 +
target/i386/tcg/translate.c | 57 +-
target/loongarch/translate.c | 6 +-
target/m68k/translate.c | 5 +-
target/microblaze/translate.c | 6 +-
target/mips/tcg/msa_translate.c | 3 -
target/mips/tcg/mxu_translate.c | 2 -
target/mips/tcg/octeon_translate.c | 4 +-
target/mips/tcg/rel6_translate.c | 2 -
target/mips/tcg/translate.c | 53 +-
target/mips/tcg/translate_addr_const.c | 1 -
target/mips/tcg/tx79_translate.c | 4 +-
target/mips/tcg/vr54xx_translate.c | 3 -
target/nios2/translate.c | 6 +-
target/openrisc/sys_helper.c | 1 +
target/openrisc/translate.c | 13 +-
target/ppc/translate.c | 17 +-
target/riscv/cpu_helper.c | 1 +
target/riscv/translate.c | 6 +-
target/rx/cpu.c | 1 +
target/rx/op_helper.c | 1 +
target/rx/translate.c | 7 +-
target/s390x/tcg/translate.c | 10 +-
target/sh4/translate.c | 8 +-
target/sparc/translate.c | 80 +-
target/tricore/cpu.c | 1 +
target/tricore/translate.c | 7 +-
target/xtensa/translate.c | 31 +-
tcg/optimize.c | 21 +-
tcg/region.c | 22 +-
tcg/tcg-common.c | 2 +
tcg/tcg-op-gvec.c | 6 +-
tcg/tcg-op-ldst.c | 1259 +++++++++++++++++
tcg/tcg-op-vec.c | 4 +-
tcg/tcg-op.c | 991 +------------
tcg/tcg.c | 359 +++--
tcg/tci.c | 96 +-
MAINTAINERS | 1 -
accel/tcg/atomic_common.c.inc | 14 +-
disas/meson.build | 4 +-
include/exec/helper-gen.h.inc | 101 ++
include/exec/helper-info.c.inc | 95 ++
include/exec/helper-proto.h.inc | 67 +
meson.build | 3 -
scripts/make-config-poison.sh | 5 +-
target/hexagon/idef-parser/idef-parser.y | 3 +-
target/loongarch/insn_trans/trans_extra.c.inc | 4 +-
.../insn_trans/trans_privileged.c.inc | 4 +-
target/riscv/insn_trans/trans_rvi.c.inc | 24 +-
tcg/aarch64/tcg-target.c.inc | 80 +-
tcg/arm/tcg-target.c.inc | 115 +-
tcg/i386/tcg-target.c.inc | 120 +-
tcg/loongarch64/tcg-target.c.inc | 45 +-
tcg/meson.build | 31 +-
tcg/mips/tcg-target.c.inc | 112 +-
tcg/ppc/tcg-target.c.inc | 151 +-
tcg/riscv/tcg-target.c.inc | 47 +-
tcg/s390x/tcg-target.c.inc | 62 +-
tcg/sparc64/tcg-target.c.inc | 48 +-
tcg/tci/tcg-target.c.inc | 53 +-
148 files changed, 5143 insertions(+), 4284 deletions(-)
delete mode 100644 include/exec/gen-icount.h
create mode 100644 include/exec/helper-gen-common.h
create mode 100644 include/exec/helper-proto-common.h
delete mode 100644 include/exec/helper-tcg.h
create mode 100644 include/exec/tlb-common.h
create mode 100644 include/exec/translation-block.h
create mode 100644 include/exec/user/guest-base.h
create mode 100644 include/tcg/debug-assert.h
create mode 100644 include/tcg/helper-info.h
create mode 100644 include/tcg/insn-start-words.h
create mode 100644 include/tcg/oversized-guest.h
create mode 100644 include/tcg/tcg-op-common.h
create mode 100644 include/tcg/tcg-op-gvec-common.h
create mode 100644 tcg/aarch64/tcg-target-reg-bits.h
create mode 100644 tcg/arm/tcg-target-reg-bits.h
create mode 100644 tcg/i386/tcg-target-reg-bits.h
create mode 100644 tcg/loongarch64/tcg-target-reg-bits.h
create mode 100644 tcg/mips/tcg-target-reg-bits.h
create mode 100644 tcg/ppc/tcg-target-reg-bits.h
create mode 100644 tcg/riscv/tcg-target-reg-bits.h
create mode 100644 tcg/s390x/tcg-target-reg-bits.h
create mode 100644 tcg/sparc64/tcg-target-reg-bits.h
create mode 100644 tcg/tci/tcg-target-reg-bits.h
rename disas.c => disas/disas.c (95%)
create mode 100644 tcg/tcg-op-ldst.c
create mode 100644 include/exec/helper-gen.h.inc
create mode 100644 include/exec/helper-info.c.inc
create mode 100644 include/exec/helper-proto.h.inc
--
2.34.1
^ permalink raw reply [flat|nested] 4+ messages in thread* [PULL v2 03/12] qemu/bitops.h: Limit rotate amounts
2023-05-03 7:20 [PATCH 00/84] tcg: Build once for system, once for user Richard Henderson
@ 2023-05-03 7:20 ` Richard Henderson
0 siblings, 0 replies; 4+ messages in thread
From: Richard Henderson @ 2023-05-03 7:20 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, philmd, marcel.apfelbaum, wangyanan55, anjo, Dickon Hood
From: Dickon Hood <dickon.hood@codethink.co.uk>
Rotates have been fixed up to only allow for reasonable rotate amounts
(ie, no rotates >7 on an 8b value etc.) This fixes a problem with riscv
vector rotate instructions.
Signed-off-by: Dickon Hood <dickon.hood@codethink.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230428144757.57530-9-lawrence.hunter@codethink.co.uk>
[rth: Mask shifts in both directions.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/qemu/bitops.h | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h
index 03213ce952..cb3526d1f4 100644
--- a/include/qemu/bitops.h
+++ b/include/qemu/bitops.h
@@ -218,7 +218,7 @@ static inline unsigned long find_first_zero_bit(const unsigned long *addr,
*/
static inline uint8_t rol8(uint8_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((8 - shift) & 7));
+ return (word << (shift & 7)) | (word >> (-shift & 7));
}
/**
@@ -228,7 +228,7 @@ static inline uint8_t rol8(uint8_t word, unsigned int shift)
*/
static inline uint8_t ror8(uint8_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((8 - shift) & 7));
+ return (word >> (shift & 7)) | (word << (-shift & 7));
}
/**
@@ -238,7 +238,7 @@ static inline uint8_t ror8(uint8_t word, unsigned int shift)
*/
static inline uint16_t rol16(uint16_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((16 - shift) & 15));
+ return (word << (shift & 15)) | (word >> (-shift & 15));
}
/**
@@ -248,7 +248,7 @@ static inline uint16_t rol16(uint16_t word, unsigned int shift)
*/
static inline uint16_t ror16(uint16_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((16 - shift) & 15));
+ return (word >> (shift & 15)) | (word << (-shift & 15));
}
/**
@@ -258,7 +258,7 @@ static inline uint16_t ror16(uint16_t word, unsigned int shift)
*/
static inline uint32_t rol32(uint32_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((32 - shift) & 31));
+ return (word << (shift & 31)) | (word >> (-shift & 31));
}
/**
@@ -268,7 +268,7 @@ static inline uint32_t rol32(uint32_t word, unsigned int shift)
*/
static inline uint32_t ror32(uint32_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((32 - shift) & 31));
+ return (word >> (shift & 31)) | (word << (-shift & 31));
}
/**
@@ -278,7 +278,7 @@ static inline uint32_t ror32(uint32_t word, unsigned int shift)
*/
static inline uint64_t rol64(uint64_t word, unsigned int shift)
{
- return (word << shift) | (word >> ((64 - shift) & 63));
+ return (word << (shift & 63)) | (word >> (-shift & 63));
}
/**
@@ -288,7 +288,7 @@ static inline uint64_t rol64(uint64_t word, unsigned int shift)
*/
static inline uint64_t ror64(uint64_t word, unsigned int shift)
{
- return (word >> shift) | (word << ((64 - shift) & 63));
+ return (word >> (shift & 63)) | (word << (-shift & 63));
}
/**
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
end of thread, other threads:[~2023-05-03 7:46 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-05-02 20:18 [PULL v2 00/12] tcg patch queue Richard Henderson
2023-05-02 20:18 ` [PULL v2 03/12] qemu/bitops.h: Limit rotate amounts Richard Henderson
2023-05-03 6:26 ` [PULL v2 00/12] tcg patch queue Richard Henderson
-- strict thread matches above, loose matches on Subject: below --
2023-05-03 7:20 [PATCH 00/84] tcg: Build once for system, once for user Richard Henderson
2023-05-03 7:20 ` [PULL v2 03/12] qemu/bitops.h: Limit rotate amounts Richard Henderson
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).