From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 12/42] target/alpha: Use MO_ALIGN where required
Date: Fri, 5 May 2023 22:24:17 +0100 [thread overview]
Message-ID: <20230505212447.374546-13-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org>
Mark all memory operations that are not already marked with UNALIGN.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/alpha/translate.c | 36 ++++++++++++++++++++----------------
1 file changed, 20 insertions(+), 16 deletions(-)
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index ffbac1c114..be8adb2526 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -2399,21 +2399,21 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
switch ((insn >> 12) & 0xF) {
case 0x0:
/* Longword physical access (hw_ldl/p) */
- tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LESL);
+ tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LESL | MO_ALIGN);
break;
case 0x1:
/* Quadword physical access (hw_ldq/p) */
- tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LEUQ);
+ tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LEUQ | MO_ALIGN);
break;
case 0x2:
/* Longword physical access with lock (hw_ldl_l/p) */
- tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LESL);
+ tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LESL | MO_ALIGN);
tcg_gen_mov_i64(cpu_lock_addr, addr);
tcg_gen_mov_i64(cpu_lock_value, va);
break;
case 0x3:
/* Quadword physical access with lock (hw_ldq_l/p) */
- tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LEUQ);
+ tcg_gen_qemu_ld_i64(va, addr, MMU_PHYS_IDX, MO_LEUQ | MO_ALIGN);
tcg_gen_mov_i64(cpu_lock_addr, addr);
tcg_gen_mov_i64(cpu_lock_value, va);
break;
@@ -2438,11 +2438,13 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
goto invalid_opc;
case 0xA:
/* Longword virtual access with protection check (hw_ldl/w) */
- tcg_gen_qemu_ld_i64(va, addr, MMU_KERNEL_IDX, MO_LESL);
+ tcg_gen_qemu_ld_i64(va, addr, MMU_KERNEL_IDX,
+ MO_LESL | MO_ALIGN);
break;
case 0xB:
/* Quadword virtual access with protection check (hw_ldq/w) */
- tcg_gen_qemu_ld_i64(va, addr, MMU_KERNEL_IDX, MO_LEUQ);
+ tcg_gen_qemu_ld_i64(va, addr, MMU_KERNEL_IDX,
+ MO_LEUQ | MO_ALIGN);
break;
case 0xC:
/* Longword virtual access with alt access mode (hw_ldl/a)*/
@@ -2453,12 +2455,14 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
case 0xE:
/* Longword virtual access with alternate access mode and
protection checks (hw_ldl/wa) */
- tcg_gen_qemu_ld_i64(va, addr, MMU_USER_IDX, MO_LESL);
+ tcg_gen_qemu_ld_i64(va, addr, MMU_USER_IDX,
+ MO_LESL | MO_ALIGN);
break;
case 0xF:
/* Quadword virtual access with alternate access mode and
protection checks (hw_ldq/wa) */
- tcg_gen_qemu_ld_i64(va, addr, MMU_USER_IDX, MO_LEUQ);
+ tcg_gen_qemu_ld_i64(va, addr, MMU_USER_IDX,
+ MO_LEUQ | MO_ALIGN);
break;
}
break;
@@ -2659,7 +2663,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
vb = load_gpr(ctx, rb);
tmp = tcg_temp_new();
tcg_gen_addi_i64(tmp, vb, disp12);
- tcg_gen_qemu_st_i64(va, tmp, MMU_PHYS_IDX, MO_LESL);
+ tcg_gen_qemu_st_i64(va, tmp, MMU_PHYS_IDX, MO_LESL | MO_ALIGN);
break;
case 0x1:
/* Quadword physical access */
@@ -2667,17 +2671,17 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
vb = load_gpr(ctx, rb);
tmp = tcg_temp_new();
tcg_gen_addi_i64(tmp, vb, disp12);
- tcg_gen_qemu_st_i64(va, tmp, MMU_PHYS_IDX, MO_LEUQ);
+ tcg_gen_qemu_st_i64(va, tmp, MMU_PHYS_IDX, MO_LEUQ | MO_ALIGN);
break;
case 0x2:
/* Longword physical access with lock */
ret = gen_store_conditional(ctx, ra, rb, disp12,
- MMU_PHYS_IDX, MO_LESL);
+ MMU_PHYS_IDX, MO_LESL | MO_ALIGN);
break;
case 0x3:
/* Quadword physical access with lock */
ret = gen_store_conditional(ctx, ra, rb, disp12,
- MMU_PHYS_IDX, MO_LEUQ);
+ MMU_PHYS_IDX, MO_LEUQ | MO_ALIGN);
break;
case 0x4:
/* Longword virtual access */
@@ -2771,11 +2775,11 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
break;
case 0x2A:
/* LDL_L */
- gen_load_int(ctx, ra, rb, disp16, MO_LESL, 0, 1);
+ gen_load_int(ctx, ra, rb, disp16, MO_LESL | MO_ALIGN, 0, 1);
break;
case 0x2B:
/* LDQ_L */
- gen_load_int(ctx, ra, rb, disp16, MO_LEUQ, 0, 1);
+ gen_load_int(ctx, ra, rb, disp16, MO_LEUQ | MO_ALIGN, 0, 1);
break;
case 0x2C:
/* STL */
@@ -2788,12 +2792,12 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
case 0x2E:
/* STL_C */
ret = gen_store_conditional(ctx, ra, rb, disp16,
- ctx->mem_idx, MO_LESL);
+ ctx->mem_idx, MO_LESL | MO_ALIGN);
break;
case 0x2F:
/* STQ_C */
ret = gen_store_conditional(ctx, ra, rb, disp16,
- ctx->mem_idx, MO_LEUQ);
+ ctx->mem_idx, MO_LEUQ | MO_ALIGN);
break;
case 0x30:
/* BR */
--
2.34.1
next prev parent reply other threads:[~2023-05-05 21:29 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-05 21:24 [PULL 00/42] tcg patch queue Richard Henderson
2023-05-05 21:24 ` [PULL 01/42] softfloat: Fix the incorrect computation in float32_exp2 Richard Henderson
2023-05-05 21:24 ` [PULL 02/42] target/avr: Finish conversion to tcg_gen_qemu_{ld,st}_* Richard Henderson
2023-05-05 21:24 ` [PULL 03/42] target/cris: Finish conversion to tcg_gen_qemu_{ld, st}_* Richard Henderson
2023-05-05 21:24 ` [PULL 04/42] target/Hexagon: " Richard Henderson
2023-05-05 21:24 ` [PULL 05/42] target/m68k: " Richard Henderson
2023-05-08 11:44 ` Laurent Vivier
2023-05-08 13:11 ` Richard Henderson
2023-05-05 21:24 ` [PULL 06/42] target/mips: " Richard Henderson
2023-05-05 21:24 ` [PULL 07/42] target/s390x: " Richard Henderson
2023-05-05 21:24 ` [PULL 08/42] target/sparc: " Richard Henderson
2023-05-05 21:24 ` [PULL 09/42] target/xtensa: " Richard Henderson
2023-05-05 21:24 ` [PULL 10/42] tcg: Remove compatability helpers for qemu ld/st Richard Henderson
2023-05-05 21:24 ` [PULL 11/42] target/alpha: Use MO_ALIGN for system UNALIGN() Richard Henderson
2023-05-05 21:24 ` Richard Henderson [this message]
2023-05-05 21:24 ` [PULL 13/42] target/alpha: Remove TARGET_ALIGNED_ONLY Richard Henderson
2023-05-05 21:24 ` [PULL 14/42] target/hppa: Use MO_ALIGN for system UNALIGN() Richard Henderson
2023-05-05 21:24 ` [PULL 15/42] target/hppa: Remove TARGET_ALIGNED_ONLY Richard Henderson
2023-05-05 21:24 ` [PULL 16/42] target/sparc: Use MO_ALIGN where required Richard Henderson
2023-05-05 21:24 ` [PULL 17/42] target/sparc: Use cpu_ld*_code_mmu Richard Henderson
2023-05-05 21:24 ` [PULL 18/42] target/sparc: Remove TARGET_ALIGNED_ONLY Richard Henderson
2023-05-05 21:24 ` [PULL 19/42] tcg/i386: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson
2023-05-05 21:24 ` [PULL 20/42] tcg/i386: Generalize multi-part load overlap test Richard Henderson
2023-05-05 21:24 ` [PULL 21/42] tcg/i386: Introduce HostAddress Richard Henderson
2023-05-05 21:24 ` [PULL 22/42] tcg/i386: Drop r0+r1 local variables from tcg_out_tlb_load Richard Henderson
2023-05-05 21:24 ` [PULL 23/42] tcg/i386: Introduce tcg_out_testi Richard Henderson
2023-05-05 21:24 ` [PULL 24/42] tcg/aarch64: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson
2023-05-05 21:24 ` [PULL 25/42] tcg/aarch64: Introduce HostAddress Richard Henderson
2023-05-05 21:24 ` [PULL 26/42] tcg/arm: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson
2023-05-05 21:24 ` [PULL 27/42] tcg/arm: Introduce HostAddress Richard Henderson
2023-05-05 21:24 ` [PULL 28/42] tcg/loongarch64: Rationalize args to tcg_out_qemu_{ld, st} Richard Henderson
2023-05-05 21:24 ` [PULL 29/42] tcg/loongarch64: Introduce HostAddress Richard Henderson
2023-05-05 21:24 ` [PULL 30/42] tcg/mips: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson
2023-05-05 21:24 ` [PULL 31/42] tcg/ppc: " Richard Henderson
2023-05-05 21:24 ` [PULL 32/42] tcg/ppc: Introduce HostAddress Richard Henderson
2023-05-05 21:24 ` [PULL 33/42] tcg/riscv: Require TCG_TARGET_REG_BITS == 64 Richard Henderson
2025-02-20 23:27 ` Philippe Mathieu-Daudé
2025-02-22 18:17 ` Richard Henderson
2025-02-24 9:24 ` Philippe Mathieu-Daudé
2023-05-05 21:24 ` [PULL 34/42] tcg/riscv: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson
2023-05-05 21:24 ` [PULL 35/42] tcg/s390x: Pass TCGType " Richard Henderson
2023-05-05 21:24 ` [PULL 36/42] tcg/s390x: Introduce HostAddress Richard Henderson
2023-05-05 21:24 ` [PULL 37/42] tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return Richard Henderson
2023-05-05 21:24 ` [PULL 38/42] tcg/sparc64: Pass TCGType to tcg_out_qemu_{ld,st} Richard Henderson
2023-05-05 21:24 ` [PULL 39/42] tcg: Move TCGLabelQemuLdst to tcg.c Richard Henderson
2023-05-05 21:24 ` [PULL 40/42] tcg: Replace REG_P with arg_loc_reg_p Richard Henderson
2023-05-05 21:24 ` [PULL 41/42] tcg: Introduce arg_slot_stk_ofs Richard Henderson
2023-05-05 21:24 ` [PULL 42/42] tcg: Widen helper_*_st[bw]_mmu val arguments Richard Henderson
2023-05-06 7:11 ` [PULL 00/42] tcg patch queue Richard Henderson
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