From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PULL 26/42] tcg/arm: Rationalize args to tcg_out_qemu_{ld,st}
Date: Fri, 5 May 2023 22:24:31 +0100 [thread overview]
Message-ID: <20230505212447.374546-27-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org>
Interpret the variable argument placement in the caller.
Pass data_type instead of is_64. We need to set this in
TCGLabelQemuLdst, so plumb this all the way through from tcg_out_op.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/arm/tcg-target.c.inc | 113 +++++++++++++++++++--------------------
1 file changed, 56 insertions(+), 57 deletions(-)
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 83c818a58b..6ce52b9612 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -1526,15 +1526,18 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
/* Record the context of a call to the out of line helper code for the slow
path for a load or store, so that we can later generate the correct
helper code. */
-static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi,
- TCGReg datalo, TCGReg datahi, TCGReg addrlo,
- TCGReg addrhi, tcg_insn_unit *raddr,
+static void add_qemu_ldst_label(TCGContext *s, bool is_ld,
+ MemOpIdx oi, TCGType type,
+ TCGReg datalo, TCGReg datahi,
+ TCGReg addrlo, TCGReg addrhi,
+ tcg_insn_unit *raddr,
tcg_insn_unit *label_ptr)
{
TCGLabelQemuLdst *label = new_ldst_label(s);
label->is_ld = is_ld;
label->oi = oi;
+ label->type = type;
label->datalo_reg = datalo;
label->datahi_reg = datahi;
label->addrlo_reg = addrlo;
@@ -1796,41 +1799,28 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg datalo,
}
#endif
-static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
+static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
+ TCGReg addrlo, TCGReg addrhi,
+ MemOpIdx oi, TCGType data_type)
{
- TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused));
- MemOpIdx oi;
- MemOp opc;
-#ifdef CONFIG_SOFTMMU
- int mem_index;
- TCGReg addend;
- tcg_insn_unit *label_ptr;
-#else
- unsigned a_bits;
-#endif
-
- datalo = *args++;
- datahi = (is64 ? *args++ : 0);
- addrlo = *args++;
- addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0);
- oi = *args++;
- opc = get_memop(oi);
+ MemOp opc = get_memop(oi);
#ifdef CONFIG_SOFTMMU
- mem_index = get_mmuidx(oi);
- addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 1);
+ TCGReg addend= tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(oi), 1);
- /* This a conditional BL only to load a pointer within this opcode into LR
- for the slow path. We will not be using the value for a tail call. */
- label_ptr = s->code_ptr;
+ /*
+ * This a conditional BL only to load a pointer within this opcode into
+ * LR for the slow path. We will not be using the value for a tail call.
+ */
+ tcg_insn_unit *label_ptr = s->code_ptr;
tcg_out_bl_imm(s, COND_NE, 0);
tcg_out_qemu_ld_index(s, opc, datalo, datahi, addrlo, addend, true);
- add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi,
- s->code_ptr, label_ptr);
+ add_qemu_ldst_label(s, true, oi, data_type, datalo, datahi,
+ addrlo, addrhi, s->code_ptr, label_ptr);
#else /* !CONFIG_SOFTMMU */
- a_bits = get_alignment_bits(opc);
+ unsigned a_bits = get_alignment_bits(opc);
if (a_bits) {
tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits);
}
@@ -1918,41 +1908,26 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg datalo,
}
#endif
-static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
+static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
+ TCGReg addrlo, TCGReg addrhi,
+ MemOpIdx oi, TCGType data_type)
{
- TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused));
- MemOpIdx oi;
- MemOp opc;
-#ifdef CONFIG_SOFTMMU
- int mem_index;
- TCGReg addend;
- tcg_insn_unit *label_ptr;
-#else
- unsigned a_bits;
-#endif
-
- datalo = *args++;
- datahi = (is64 ? *args++ : 0);
- addrlo = *args++;
- addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0);
- oi = *args++;
- opc = get_memop(oi);
+ MemOp opc = get_memop(oi);
#ifdef CONFIG_SOFTMMU
- mem_index = get_mmuidx(oi);
- addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, mem_index, 0);
+ TCGReg addend = tcg_out_tlb_read(s, addrlo, addrhi, opc, get_mmuidx(oi), 0);
tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi,
addrlo, addend, true);
/* The conditional call must come last, as we're going to return here. */
- label_ptr = s->code_ptr;
+ tcg_insn_unit *label_ptr = s->code_ptr;
tcg_out_bl_imm(s, COND_NE, 0);
- add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi,
- s->code_ptr, label_ptr);
+ add_qemu_ldst_label(s, false, oi, data_type, datalo, datahi,
+ addrlo, addrhi, s->code_ptr, label_ptr);
#else /* !CONFIG_SOFTMMU */
- a_bits = get_alignment_bits(opc);
+ unsigned a_bits = get_alignment_bits(opc);
if (a_bits) {
tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits);
}
@@ -2245,16 +2220,40 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_qemu_ld_i32:
- tcg_out_qemu_ld(s, args, 0);
+ if (TARGET_LONG_BITS == 32) {
+ tcg_out_qemu_ld(s, args[0], -1, args[1], -1,
+ args[2], TCG_TYPE_I32);
+ } else {
+ tcg_out_qemu_ld(s, args[0], -1, args[1], args[2],
+ args[3], TCG_TYPE_I32);
+ }
break;
case INDEX_op_qemu_ld_i64:
- tcg_out_qemu_ld(s, args, 1);
+ if (TARGET_LONG_BITS == 32) {
+ tcg_out_qemu_ld(s, args[0], args[1], args[2], -1,
+ args[3], TCG_TYPE_I64);
+ } else {
+ tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3],
+ args[4], TCG_TYPE_I64);
+ }
break;
case INDEX_op_qemu_st_i32:
- tcg_out_qemu_st(s, args, 0);
+ if (TARGET_LONG_BITS == 32) {
+ tcg_out_qemu_st(s, args[0], -1, args[1], -1,
+ args[2], TCG_TYPE_I32);
+ } else {
+ tcg_out_qemu_st(s, args[0], -1, args[1], args[2],
+ args[3], TCG_TYPE_I32);
+ }
break;
case INDEX_op_qemu_st_i64:
- tcg_out_qemu_st(s, args, 1);
+ if (TARGET_LONG_BITS == 32) {
+ tcg_out_qemu_st(s, args[0], args[1], args[2], -1,
+ args[3], TCG_TYPE_I64);
+ } else {
+ tcg_out_qemu_st(s, args[0], args[1], args[2], args[3],
+ args[4], TCG_TYPE_I64);
+ }
break;
case INDEX_op_bswap16_i32:
--
2.34.1
next prev parent reply other threads:[~2023-05-05 21:27 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-05 21:24 [PULL 00/42] tcg patch queue Richard Henderson
2023-05-05 21:24 ` [PULL 01/42] softfloat: Fix the incorrect computation in float32_exp2 Richard Henderson
2023-05-05 21:24 ` [PULL 02/42] target/avr: Finish conversion to tcg_gen_qemu_{ld,st}_* Richard Henderson
2023-05-05 21:24 ` [PULL 03/42] target/cris: Finish conversion to tcg_gen_qemu_{ld, st}_* Richard Henderson
2023-05-05 21:24 ` [PULL 04/42] target/Hexagon: " Richard Henderson
2023-05-05 21:24 ` [PULL 05/42] target/m68k: " Richard Henderson
2023-05-08 11:44 ` Laurent Vivier
2023-05-08 13:11 ` Richard Henderson
2023-05-05 21:24 ` [PULL 06/42] target/mips: " Richard Henderson
2023-05-05 21:24 ` [PULL 07/42] target/s390x: " Richard Henderson
2023-05-05 21:24 ` [PULL 08/42] target/sparc: " Richard Henderson
2023-05-05 21:24 ` [PULL 09/42] target/xtensa: " Richard Henderson
2023-05-05 21:24 ` [PULL 10/42] tcg: Remove compatability helpers for qemu ld/st Richard Henderson
2023-05-05 21:24 ` [PULL 11/42] target/alpha: Use MO_ALIGN for system UNALIGN() Richard Henderson
2023-05-05 21:24 ` [PULL 12/42] target/alpha: Use MO_ALIGN where required Richard Henderson
2023-05-05 21:24 ` [PULL 13/42] target/alpha: Remove TARGET_ALIGNED_ONLY Richard Henderson
2023-05-05 21:24 ` [PULL 14/42] target/hppa: Use MO_ALIGN for system UNALIGN() Richard Henderson
2023-05-05 21:24 ` [PULL 15/42] target/hppa: Remove TARGET_ALIGNED_ONLY Richard Henderson
2023-05-05 21:24 ` [PULL 16/42] target/sparc: Use MO_ALIGN where required Richard Henderson
2023-05-05 21:24 ` [PULL 17/42] target/sparc: Use cpu_ld*_code_mmu Richard Henderson
2023-05-05 21:24 ` [PULL 18/42] target/sparc: Remove TARGET_ALIGNED_ONLY Richard Henderson
2023-05-05 21:24 ` [PULL 19/42] tcg/i386: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson
2023-05-05 21:24 ` [PULL 20/42] tcg/i386: Generalize multi-part load overlap test Richard Henderson
2023-05-05 21:24 ` [PULL 21/42] tcg/i386: Introduce HostAddress Richard Henderson
2023-05-05 21:24 ` [PULL 22/42] tcg/i386: Drop r0+r1 local variables from tcg_out_tlb_load Richard Henderson
2023-05-05 21:24 ` [PULL 23/42] tcg/i386: Introduce tcg_out_testi Richard Henderson
2023-05-05 21:24 ` [PULL 24/42] tcg/aarch64: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson
2023-05-05 21:24 ` [PULL 25/42] tcg/aarch64: Introduce HostAddress Richard Henderson
2023-05-05 21:24 ` Richard Henderson [this message]
2023-05-05 21:24 ` [PULL 27/42] tcg/arm: " Richard Henderson
2023-05-05 21:24 ` [PULL 28/42] tcg/loongarch64: Rationalize args to tcg_out_qemu_{ld, st} Richard Henderson
2023-05-05 21:24 ` [PULL 29/42] tcg/loongarch64: Introduce HostAddress Richard Henderson
2023-05-05 21:24 ` [PULL 30/42] tcg/mips: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson
2023-05-05 21:24 ` [PULL 31/42] tcg/ppc: " Richard Henderson
2023-05-05 21:24 ` [PULL 32/42] tcg/ppc: Introduce HostAddress Richard Henderson
2023-05-05 21:24 ` [PULL 33/42] tcg/riscv: Require TCG_TARGET_REG_BITS == 64 Richard Henderson
2025-02-20 23:27 ` Philippe Mathieu-Daudé
2025-02-22 18:17 ` Richard Henderson
2025-02-24 9:24 ` Philippe Mathieu-Daudé
2023-05-05 21:24 ` [PULL 34/42] tcg/riscv: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson
2023-05-05 21:24 ` [PULL 35/42] tcg/s390x: Pass TCGType " Richard Henderson
2023-05-05 21:24 ` [PULL 36/42] tcg/s390x: Introduce HostAddress Richard Henderson
2023-05-05 21:24 ` [PULL 37/42] tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return Richard Henderson
2023-05-05 21:24 ` [PULL 38/42] tcg/sparc64: Pass TCGType to tcg_out_qemu_{ld,st} Richard Henderson
2023-05-05 21:24 ` [PULL 39/42] tcg: Move TCGLabelQemuLdst to tcg.c Richard Henderson
2023-05-05 21:24 ` [PULL 40/42] tcg: Replace REG_P with arg_loc_reg_p Richard Henderson
2023-05-05 21:24 ` [PULL 41/42] tcg: Introduce arg_slot_stk_ofs Richard Henderson
2023-05-05 21:24 ` [PULL 42/42] tcg: Widen helper_*_st[bw]_mmu val arguments Richard Henderson
2023-05-06 7:11 ` [PULL 00/42] tcg patch queue Richard Henderson
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