From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Anton Johansson <anjo@rev.ng>
Subject: [PULL 05/42] target/m68k: Finish conversion to tcg_gen_qemu_{ld, st}_*
Date: Fri, 5 May 2023 22:24:10 +0100 [thread overview]
Message-ID: <20230505212447.374546-6-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230505212447.374546-1-richard.henderson@linaro.org>
Convert away from the old interface with the implicit
MemOp argument.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230502135741.1158035-5-richard.henderson@linaro.org>
---
target/m68k/translate.c | 76 ++++++++++++++---------------------------
1 file changed, 25 insertions(+), 51 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 422f4652f1..744eb3748b 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -304,23 +304,14 @@ static inline void gen_addr_fault(DisasContext *s)
static inline TCGv gen_load(DisasContext *s, int opsize, TCGv addr,
int sign, int index)
{
- TCGv tmp;
- tmp = tcg_temp_new_i32();
- switch(opsize) {
+ TCGv tmp = tcg_temp_new_i32();
+
+ switch (opsize) {
case OS_BYTE:
- if (sign)
- tcg_gen_qemu_ld8s(tmp, addr, index);
- else
- tcg_gen_qemu_ld8u(tmp, addr, index);
- break;
case OS_WORD:
- if (sign)
- tcg_gen_qemu_ld16s(tmp, addr, index);
- else
- tcg_gen_qemu_ld16u(tmp, addr, index);
- break;
case OS_LONG:
- tcg_gen_qemu_ld32u(tmp, addr, index);
+ tcg_gen_qemu_ld_tl(tmp, addr, index,
+ opsize | (sign ? MO_SIGN : 0) | MO_TE);
break;
default:
g_assert_not_reached();
@@ -332,15 +323,11 @@ static inline TCGv gen_load(DisasContext *s, int opsize, TCGv addr,
static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val,
int index)
{
- switch(opsize) {
+ switch (opsize) {
case OS_BYTE:
- tcg_gen_qemu_st8(val, addr, index);
- break;
case OS_WORD:
- tcg_gen_qemu_st16(val, addr, index);
- break;
case OS_LONG:
- tcg_gen_qemu_st32(val, addr, index);
+ tcg_gen_qemu_st_tl(val, addr, index, opsize | MO_TE);
break;
default:
g_assert_not_reached();
@@ -971,23 +958,16 @@ static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
tmp = tcg_temp_new();
switch (opsize) {
case OS_BYTE:
- tcg_gen_qemu_ld8s(tmp, addr, index);
- gen_helper_exts32(cpu_env, fp, tmp);
- break;
case OS_WORD:
- tcg_gen_qemu_ld16s(tmp, addr, index);
- gen_helper_exts32(cpu_env, fp, tmp);
- break;
- case OS_LONG:
- tcg_gen_qemu_ld32u(tmp, addr, index);
+ tcg_gen_qemu_ld_tl(tmp, addr, index, opsize | MO_SIGN | MO_TE);
gen_helper_exts32(cpu_env, fp, tmp);
break;
case OS_SINGLE:
- tcg_gen_qemu_ld32u(tmp, addr, index);
+ tcg_gen_qemu_ld_tl(tmp, addr, index, MO_TEUL);
gen_helper_extf32(cpu_env, fp, tmp);
break;
case OS_DOUBLE:
- tcg_gen_qemu_ld64(t64, addr, index);
+ tcg_gen_qemu_ld_i64(t64, addr, index, MO_TEUQ);
gen_helper_extf64(cpu_env, fp, t64);
break;
case OS_EXTENDED:
@@ -995,11 +975,11 @@ static void gen_load_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
gen_exception(s, s->base.pc_next, EXCP_FP_UNIMP);
break;
}
- tcg_gen_qemu_ld32u(tmp, addr, index);
+ tcg_gen_qemu_ld_i32(tmp, addr, index, MO_TEUL);
tcg_gen_shri_i32(tmp, tmp, 16);
tcg_gen_st16_i32(tmp, fp, offsetof(FPReg, l.upper));
tcg_gen_addi_i32(tmp, addr, 4);
- tcg_gen_qemu_ld64(t64, tmp, index);
+ tcg_gen_qemu_ld_i64(t64, tmp, index, MO_TEUQ);
tcg_gen_st_i64(t64, fp, offsetof(FPReg, l.lower));
break;
case OS_PACKED:
@@ -1024,24 +1004,18 @@ static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
tmp = tcg_temp_new();
switch (opsize) {
case OS_BYTE:
- gen_helper_reds32(tmp, cpu_env, fp);
- tcg_gen_qemu_st8(tmp, addr, index);
- break;
case OS_WORD:
- gen_helper_reds32(tmp, cpu_env, fp);
- tcg_gen_qemu_st16(tmp, addr, index);
- break;
case OS_LONG:
gen_helper_reds32(tmp, cpu_env, fp);
- tcg_gen_qemu_st32(tmp, addr, index);
+ tcg_gen_qemu_st_tl(tmp, addr, index, opsize | MO_TE);
break;
case OS_SINGLE:
gen_helper_redf32(tmp, cpu_env, fp);
- tcg_gen_qemu_st32(tmp, addr, index);
+ tcg_gen_qemu_st_tl(tmp, addr, index, MO_TEUL);
break;
case OS_DOUBLE:
gen_helper_redf64(t64, cpu_env, fp);
- tcg_gen_qemu_st64(t64, addr, index);
+ tcg_gen_qemu_st_i64(t64, addr, index, MO_TEUQ);
break;
case OS_EXTENDED:
if (m68k_feature(s->env, M68K_FEATURE_CF_FPU)) {
@@ -1050,10 +1024,10 @@ static void gen_store_fp(DisasContext *s, int opsize, TCGv addr, TCGv_ptr fp,
}
tcg_gen_ld16u_i32(tmp, fp, offsetof(FPReg, l.upper));
tcg_gen_shli_i32(tmp, tmp, 16);
- tcg_gen_qemu_st32(tmp, addr, index);
+ tcg_gen_qemu_st_i32(tmp, addr, index, MO_TEUL);
tcg_gen_addi_i32(tmp, addr, 4);
tcg_gen_ld_i64(t64, fp, offsetof(FPReg, l.lower));
- tcg_gen_qemu_st64(t64, tmp, index);
+ tcg_gen_qemu_st_i64(t64, tmp, index, MO_TEUQ);
break;
case OS_PACKED:
/*
@@ -2079,14 +2053,14 @@ DISAS_INSN(movep)
if (insn & 0x80) {
for ( ; i > 0 ; i--) {
tcg_gen_shri_i32(dbuf, reg, (i - 1) * 8);
- tcg_gen_qemu_st8(dbuf, abuf, IS_USER(s));
+ tcg_gen_qemu_st_i32(dbuf, abuf, IS_USER(s), MO_UB);
if (i > 1) {
tcg_gen_addi_i32(abuf, abuf, 2);
}
}
} else {
for ( ; i > 0 ; i--) {
- tcg_gen_qemu_ld8u(dbuf, abuf, IS_USER(s));
+ tcg_gen_qemu_ld_tl(dbuf, abuf, IS_USER(s), MO_UB);
tcg_gen_deposit_i32(reg, reg, dbuf, (i - 1) * 8, 8);
if (i > 1) {
tcg_gen_addi_i32(abuf, abuf, 2);
@@ -4337,14 +4311,14 @@ static void m68k_copy_line(TCGv dst, TCGv src, int index)
t1 = tcg_temp_new_i64();
tcg_gen_andi_i32(addr, src, ~15);
- tcg_gen_qemu_ld64(t0, addr, index);
+ tcg_gen_qemu_ld_i64(t0, addr, index, MO_TEUQ);
tcg_gen_addi_i32(addr, addr, 8);
- tcg_gen_qemu_ld64(t1, addr, index);
+ tcg_gen_qemu_ld_i64(t1, addr, index, MO_TEUQ);
tcg_gen_andi_i32(addr, dst, ~15);
- tcg_gen_qemu_st64(t0, addr, index);
+ tcg_gen_qemu_st_i64(t0, addr, index, MO_TEUQ);
tcg_gen_addi_i32(addr, addr, 8);
- tcg_gen_qemu_st64(t1, addr, index);
+ tcg_gen_qemu_st_i64(t1, addr, index, MO_TEUQ);
}
DISAS_INSN(move16_reg)
@@ -4767,7 +4741,7 @@ static void gen_qemu_store_fcr(DisasContext *s, TCGv addr, int reg)
tmp = tcg_temp_new();
gen_load_fcr(s, tmp, reg);
- tcg_gen_qemu_st32(tmp, addr, index);
+ tcg_gen_qemu_st_tl(tmp, addr, index, MO_TEUL);
}
static void gen_qemu_load_fcr(DisasContext *s, TCGv addr, int reg)
@@ -4776,7 +4750,7 @@ static void gen_qemu_load_fcr(DisasContext *s, TCGv addr, int reg)
TCGv tmp;
tmp = tcg_temp_new();
- tcg_gen_qemu_ld32u(tmp, addr, index);
+ tcg_gen_qemu_ld_tl(tmp, addr, index, MO_TEUL);
gen_store_fcr(s, tmp, reg);
}
--
2.34.1
next prev parent reply other threads:[~2023-05-05 21:26 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-05 21:24 [PULL 00/42] tcg patch queue Richard Henderson
2023-05-05 21:24 ` [PULL 01/42] softfloat: Fix the incorrect computation in float32_exp2 Richard Henderson
2023-05-05 21:24 ` [PULL 02/42] target/avr: Finish conversion to tcg_gen_qemu_{ld,st}_* Richard Henderson
2023-05-05 21:24 ` [PULL 03/42] target/cris: Finish conversion to tcg_gen_qemu_{ld, st}_* Richard Henderson
2023-05-05 21:24 ` [PULL 04/42] target/Hexagon: " Richard Henderson
2023-05-05 21:24 ` Richard Henderson [this message]
2023-05-08 11:44 ` [PULL 05/42] target/m68k: " Laurent Vivier
2023-05-08 13:11 ` Richard Henderson
2023-05-05 21:24 ` [PULL 06/42] target/mips: " Richard Henderson
2023-05-05 21:24 ` [PULL 07/42] target/s390x: " Richard Henderson
2023-05-05 21:24 ` [PULL 08/42] target/sparc: " Richard Henderson
2023-05-05 21:24 ` [PULL 09/42] target/xtensa: " Richard Henderson
2023-05-05 21:24 ` [PULL 10/42] tcg: Remove compatability helpers for qemu ld/st Richard Henderson
2023-05-05 21:24 ` [PULL 11/42] target/alpha: Use MO_ALIGN for system UNALIGN() Richard Henderson
2023-05-05 21:24 ` [PULL 12/42] target/alpha: Use MO_ALIGN where required Richard Henderson
2023-05-05 21:24 ` [PULL 13/42] target/alpha: Remove TARGET_ALIGNED_ONLY Richard Henderson
2023-05-05 21:24 ` [PULL 14/42] target/hppa: Use MO_ALIGN for system UNALIGN() Richard Henderson
2023-05-05 21:24 ` [PULL 15/42] target/hppa: Remove TARGET_ALIGNED_ONLY Richard Henderson
2023-05-05 21:24 ` [PULL 16/42] target/sparc: Use MO_ALIGN where required Richard Henderson
2023-05-05 21:24 ` [PULL 17/42] target/sparc: Use cpu_ld*_code_mmu Richard Henderson
2023-05-05 21:24 ` [PULL 18/42] target/sparc: Remove TARGET_ALIGNED_ONLY Richard Henderson
2023-05-05 21:24 ` [PULL 19/42] tcg/i386: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson
2023-05-05 21:24 ` [PULL 20/42] tcg/i386: Generalize multi-part load overlap test Richard Henderson
2023-05-05 21:24 ` [PULL 21/42] tcg/i386: Introduce HostAddress Richard Henderson
2023-05-05 21:24 ` [PULL 22/42] tcg/i386: Drop r0+r1 local variables from tcg_out_tlb_load Richard Henderson
2023-05-05 21:24 ` [PULL 23/42] tcg/i386: Introduce tcg_out_testi Richard Henderson
2023-05-05 21:24 ` [PULL 24/42] tcg/aarch64: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson
2023-05-05 21:24 ` [PULL 25/42] tcg/aarch64: Introduce HostAddress Richard Henderson
2023-05-05 21:24 ` [PULL 26/42] tcg/arm: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson
2023-05-05 21:24 ` [PULL 27/42] tcg/arm: Introduce HostAddress Richard Henderson
2023-05-05 21:24 ` [PULL 28/42] tcg/loongarch64: Rationalize args to tcg_out_qemu_{ld, st} Richard Henderson
2023-05-05 21:24 ` [PULL 29/42] tcg/loongarch64: Introduce HostAddress Richard Henderson
2023-05-05 21:24 ` [PULL 30/42] tcg/mips: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson
2023-05-05 21:24 ` [PULL 31/42] tcg/ppc: " Richard Henderson
2023-05-05 21:24 ` [PULL 32/42] tcg/ppc: Introduce HostAddress Richard Henderson
2023-05-05 21:24 ` [PULL 33/42] tcg/riscv: Require TCG_TARGET_REG_BITS == 64 Richard Henderson
2025-02-20 23:27 ` Philippe Mathieu-Daudé
2025-02-22 18:17 ` Richard Henderson
2025-02-24 9:24 ` Philippe Mathieu-Daudé
2023-05-05 21:24 ` [PULL 34/42] tcg/riscv: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson
2023-05-05 21:24 ` [PULL 35/42] tcg/s390x: Pass TCGType " Richard Henderson
2023-05-05 21:24 ` [PULL 36/42] tcg/s390x: Introduce HostAddress Richard Henderson
2023-05-05 21:24 ` [PULL 37/42] tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return Richard Henderson
2023-05-05 21:24 ` [PULL 38/42] tcg/sparc64: Pass TCGType to tcg_out_qemu_{ld,st} Richard Henderson
2023-05-05 21:24 ` [PULL 39/42] tcg: Move TCGLabelQemuLdst to tcg.c Richard Henderson
2023-05-05 21:24 ` [PULL 40/42] tcg: Replace REG_P with arg_loc_reg_p Richard Henderson
2023-05-05 21:24 ` [PULL 41/42] tcg: Introduce arg_slot_stk_ofs Richard Henderson
2023-05-05 21:24 ` [PULL 42/42] tcg: Widen helper_*_st[bw]_mmu val arguments Richard Henderson
2023-05-06 7:11 ` [PULL 00/42] tcg patch queue Richard Henderson
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