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From: Stafford Horne <shorne@gmail.com>
To: QEMU Development <qemu-devel@nongnu.org>
Cc: Linux OpenRISC <linux-openrisc@vger.kernel.org>,
	Stafford Horne <shorne@gmail.com>
Subject: [PATCH v2 2/3] target/openrisc: Set PC to cpu state on FPU exception
Date: Wed, 10 May 2023 16:32:27 +0100	[thread overview]
Message-ID: <20230510153228.264954-3-shorne@gmail.com> (raw)
In-Reply-To: <20230510153228.264954-1-shorne@gmail.com>

Store the PC to ensure the correct value can be read in the exception
handler.

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
Since v1:
 - Use function do_fpe (similar to do_range) to raise exception.

 target/openrisc/fpu_helper.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c
index f9e34fa2cc..8b81d2f62f 100644
--- a/target/openrisc/fpu_helper.c
+++ b/target/openrisc/fpu_helper.c
@@ -20,8 +20,8 @@
 
 #include "qemu/osdep.h"
 #include "cpu.h"
+#include "exec/exec-all.h"
 #include "exec/helper-proto.h"
-#include "exception.h"
 #include "fpu/softfloat.h"
 
 static int ieee_ex_to_openrisc(int fexcp)
@@ -45,6 +45,15 @@ static int ieee_ex_to_openrisc(int fexcp)
     return ret;
 }
 
+static G_NORETURN
+void do_fpe(CPUOpenRISCState *env, uintptr_t pc)
+{
+    CPUState *cs = env_cpu(env);
+
+    cs->exception_index = EXCP_FPE;
+    cpu_loop_exit_restore(cs, pc);
+}
+
 void HELPER(update_fpcsr)(CPUOpenRISCState *env)
 {
     int tmp = get_float_exception_flags(&env->fp_status);
@@ -55,7 +64,7 @@ void HELPER(update_fpcsr)(CPUOpenRISCState *env)
         if (tmp) {
             env->fpcsr |= tmp;
             if (env->fpcsr & FPCSR_FPEE) {
-                helper_exception(env, EXCP_FPE);
+                do_fpe(env, GETPC());
             }
         }
     }
-- 
2.39.1



  parent reply	other threads:[~2023-05-10 15:33 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-10 15:32 [PATCH v2 0/3] OpenRISC updates for user space FPU Stafford Horne
2023-05-10 15:32 ` [PATCH v2 1/3] target/openrisc: Allow fpcsr access in user mode Stafford Horne
2023-05-10 16:13   ` Richard Henderson
2023-05-11 14:25     ` Stafford Horne
2023-05-10 15:32 ` Stafford Horne [this message]
2023-05-10 16:13   ` [PATCH v2 2/3] target/openrisc: Set PC to cpu state on FPU exception Richard Henderson
2023-05-10 15:32 ` [PATCH v2 3/3] target/openrisc: Setup FPU for detecting tininess before rounding Stafford Horne
2023-05-10 16:16   ` Richard Henderson
2023-05-11 14:33     ` Stafford Horne

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