From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Alex Bennée" <alex.bennee@linaro.org>,
"Daniel Henrique Barboza" <danielhb413@gmail.com>
Subject: [PULL 27/53] tcg/ppc: Convert tcg_out_qemu_{ld,st}_slow_path
Date: Thu, 11 May 2023 09:04:24 +0100 [thread overview]
Message-ID: <20230511080450.860923-28-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org>
Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret,
and tcg_out_st_helper_args.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/ppc/tcg-target.c.inc | 88 ++++++++++++----------------------------
1 file changed, 26 insertions(+), 62 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 0469e299a0..4c479fdece 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -2003,44 +2003,38 @@ static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = {
[MO_BEUQ] = helper_be_stq_mmu,
};
+static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int arg)
+{
+ if (arg < 0) {
+ arg = TCG_REG_TMP1;
+ }
+ tcg_out32(s, MFSPR | RT(arg) | LR);
+ return arg;
+}
+
+/*
+ * For the purposes of ppc32 sorting 4 input registers into 4 argument
+ * registers, there is an outside chance we would require 3 temps.
+ * Because of constraints, no inputs are in r3, and env will not be
+ * placed into r3 until after the sorting is done, and is thus free.
+ */
+static const TCGLdstHelperParam ldst_helper_param = {
+ .ra_gen = ldst_ra_gen,
+ .ntmp = 3,
+ .tmp = { TCG_REG_TMP1, TCG_REG_R0, TCG_REG_R3 }
+};
+
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
{
- MemOpIdx oi = lb->oi;
- MemOp opc = get_memop(oi);
- TCGReg hi, lo, arg = TCG_REG_R3;
+ MemOp opc = get_memop(lb->oi);
if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
return false;
}
- tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
-
- lo = lb->addrlo_reg;
- hi = lb->addrhi_reg;
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
- arg |= (TCG_TARGET_CALL_ARG_I64 == TCG_CALL_ARG_EVEN);
- tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
- tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
- } else {
- /* If the address needed to be zero-extended, we'll have already
- placed it in R4. The only remaining case is 64-bit guest. */
- tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
- }
-
- tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
- tcg_out32(s, MFSPR | RT(arg) | LR);
-
+ tcg_out_ld_helper_args(s, lb, &ldst_helper_param);
tcg_out_call_int(s, LK, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]);
-
- lo = lb->datalo_reg;
- hi = lb->datahi_reg;
- if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
- tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4);
- tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3);
- } else {
- tcg_out_movext(s, lb->type, lo,
- TCG_TYPE_REG, opc & MO_SSIZE, TCG_REG_R3);
- }
+ tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param);
tcg_out_b(s, 0, lb->raddr);
return true;
@@ -2048,43 +2042,13 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
{
- MemOpIdx oi = lb->oi;
- MemOp opc = get_memop(oi);
- MemOp s_bits = opc & MO_SIZE;
- TCGReg hi, lo, arg = TCG_REG_R3;
+ MemOp opc = get_memop(lb->oi);
if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
return false;
}
- tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
-
- lo = lb->addrlo_reg;
- hi = lb->addrhi_reg;
- if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
- arg |= (TCG_TARGET_CALL_ARG_I64 == TCG_CALL_ARG_EVEN);
- tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
- tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
- } else {
- /* If the address needed to be zero-extended, we'll have already
- placed it in R4. The only remaining case is 64-bit guest. */
- tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
- }
-
- lo = lb->datalo_reg;
- hi = lb->datahi_reg;
- if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
- arg |= (TCG_TARGET_CALL_ARG_I64 == TCG_CALL_ARG_EVEN);
- tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
- tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
- } else {
- tcg_out_movext(s, s_bits == MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32,
- arg++, lb->type, s_bits, lo);
- }
-
- tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
- tcg_out32(s, MFSPR | RT(arg) | LR);
-
+ tcg_out_st_helper_args(s, lb, &ldst_helper_param);
tcg_out_call_int(s, LK, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
tcg_out_b(s, 0, lb->raddr);
--
2.34.1
next prev parent reply other threads:[~2023-05-11 8:14 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-11 8:03 [PULL 00/53] tcg patch queue Richard Henderson
2023-05-11 8:03 ` [PULL 01/53] target/m68k: Fix gen_load_fp for OS_LONG Richard Henderson
2023-05-11 8:03 ` [PULL 02/53] accel/tcg: Fix atomic_mmu_lookup for reads Richard Henderson
2023-05-11 8:04 ` [PULL 03/53] disas: Fix tabs and braces in disas.c Richard Henderson
2023-05-11 8:04 ` [PULL 04/53] disas: Move disas.c to disas/ Richard Henderson
2023-05-11 8:04 ` [PULL 05/53] disas: Remove target_ulong from the interface Richard Henderson
2023-05-11 8:04 ` [PULL 06/53] disas: Remove target-specific headers Richard Henderson
2023-05-11 8:04 ` [PULL 07/53] disas: Move softmmu specific code to separate file Richard Henderson
2023-05-11 8:04 ` [PULL 08/53] disas: Move disas.c into the target-independent source set Richard Henderson
2023-05-11 8:04 ` [PULL 09/53] cpu: expose qemu_cpu_list_lock for lock-guard use Richard Henderson
2023-05-11 8:04 ` [PULL 10/53] accel/tcg/tcg-accel-ops-rr: ensure fairness with icount Richard Henderson
2023-05-11 8:04 ` [PULL 11/53] tcg/i386: Introduce prepare_host_addr Richard Henderson
2023-05-11 8:04 ` [PULL 12/53] tcg/i386: Use indexed addressing for softmmu fast path Richard Henderson
2023-05-11 8:04 ` [PULL 13/53] tcg/aarch64: Introduce prepare_host_addr Richard Henderson
2023-05-11 8:04 ` [PULL 14/53] tcg/arm: " Richard Henderson
2023-05-11 8:04 ` [PULL 15/53] tcg/loongarch64: " Richard Henderson
2023-05-11 8:04 ` [PULL 16/53] tcg/mips: " Richard Henderson
2023-05-11 8:04 ` [PULL 17/53] tcg/ppc: " Richard Henderson
2023-05-11 8:04 ` [PULL 18/53] tcg/riscv: " Richard Henderson
2023-05-11 8:04 ` [PULL 19/53] tcg/s390x: " Richard Henderson
2023-05-11 8:04 ` [PULL 20/53] tcg: Add routines for calling slow-path helpers Richard Henderson
2023-05-11 8:04 ` [PULL 21/53] tcg/i386: Convert tcg_out_qemu_ld_slow_path Richard Henderson
2023-05-11 8:04 ` [PULL 22/53] tcg/i386: Convert tcg_out_qemu_st_slow_path Richard Henderson
2023-05-11 8:04 ` [PULL 23/53] tcg/aarch64: Convert tcg_out_qemu_{ld,st}_slow_path Richard Henderson
2023-05-11 8:04 ` [PULL 24/53] tcg/arm: " Richard Henderson
2023-05-11 8:04 ` [PULL 25/53] tcg/loongarch64: " Richard Henderson
2023-05-11 8:04 ` [PULL 26/53] tcg/mips: " Richard Henderson
2023-05-11 8:04 ` Richard Henderson [this message]
2023-05-11 8:04 ` [PULL 28/53] tcg/riscv: " Richard Henderson
2023-05-11 8:04 ` [PULL 29/53] tcg/s390x: " Richard Henderson
2023-05-11 8:04 ` [PULL 30/53] tcg/loongarch64: Simplify constraints on qemu_ld/st Richard Henderson
2023-05-11 8:04 ` [PULL 31/53] tcg/mips: Remove MO_BSWAP handling Richard Henderson
2023-05-11 8:04 ` [PULL 32/53] tcg/mips: Reorg tlb load within prepare_host_addr Richard Henderson
2023-05-11 8:04 ` [PULL 33/53] tcg/mips: Simplify constraints on qemu_ld/st Richard Henderson
2023-05-11 8:04 ` [PULL 34/53] tcg/ppc: Reorg tcg_out_tlb_read Richard Henderson
2023-05-11 8:04 ` [PULL 35/53] tcg/ppc: Adjust constraints on qemu_ld/st Richard Henderson
2023-05-11 8:04 ` [PULL 36/53] tcg/ppc: Remove unused constraints A, B, C, D Richard Henderson
2023-05-11 8:04 ` [PULL 37/53] tcg/ppc: Remove unused constraint J Richard Henderson
2023-05-11 8:04 ` [PULL 38/53] tcg/riscv: Simplify constraints on qemu_ld/st Richard Henderson
2023-05-11 8:04 ` [PULL 39/53] tcg/s390x: Use ALGFR in constructing softmmu host address Richard Henderson
2023-05-11 8:04 ` [PULL 40/53] tcg/s390x: Simplify constraints on qemu_ld/st Richard Henderson
2023-05-11 8:04 ` [PULL 41/53] target/mips: Add MO_ALIGN to gen_llwp, gen_scwp Richard Henderson
2023-05-11 8:04 ` [PULL 42/53] target/mips: Add missing default_tcg_memop_mask Richard Henderson
2023-05-11 8:04 ` [PULL 43/53] target/mips: Use MO_ALIGN instead of 0 Richard Henderson
2023-05-11 8:04 ` [PULL 44/53] target/mips: Remove TARGET_ALIGNED_ONLY Richard Henderson
2023-05-11 8:04 ` [PULL 45/53] target/nios2: " Richard Henderson
2023-05-11 8:04 ` [PULL 46/53] target/sh4: Use MO_ALIGN where required Richard Henderson
2023-05-11 8:04 ` [PULL 47/53] target/sh4: Remove TARGET_ALIGNED_ONLY Richard Henderson
2023-05-11 8:04 ` [PULL 48/53] tcg: " Richard Henderson
2023-05-11 8:04 ` [PULL 49/53] accel/tcg: Add cpu_in_serial_context Richard Henderson
2023-05-11 8:04 ` [PULL 50/53] accel/tcg: Introduce tlb_read_idx Richard Henderson
2023-05-11 8:04 ` [PULL 51/53] accel/tcg: Reorg system mode load helpers Richard Henderson
2023-05-11 8:04 ` [PULL 52/53] accel/tcg: Reorg system mode store helpers Richard Henderson
2023-05-11 8:04 ` [PULL 53/53] target/loongarch: Do not include tcg-ldst.h Richard Henderson
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