From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 42/53] target/mips: Add missing default_tcg_memop_mask
Date: Thu, 11 May 2023 09:04:39 +0100 [thread overview]
Message-ID: <20230511080450.860923-43-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org>
Memory operations that are not already aligned, or otherwise
marked up, require addition of ctx->default_tcg_memop_mask.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/mips/tcg/mxu_translate.c | 3 ++-
target/mips/tcg/micromips_translate.c.inc | 24 ++++++++++++++--------
target/mips/tcg/mips16e_translate.c.inc | 18 ++++++++++------
target/mips/tcg/nanomips_translate.c.inc | 25 +++++++++++------------
4 files changed, 42 insertions(+), 28 deletions(-)
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index bdd20709c0..be038b5f07 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -831,7 +831,8 @@ static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx)
tcg_gen_ori_tl(t1, t1, 0xFFFFF000);
}
tcg_gen_add_tl(t1, t0, t1);
- tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, MO_TESL ^ (sel * MO_BSWAP));
+ tcg_gen_qemu_ld_tl(t1, t1, ctx->mem_idx, (MO_TESL ^ (sel * MO_BSWAP)) |
+ ctx->default_tcg_memop_mask);
gen_store_mxu_gpr(t1, XRa);
}
diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc
index e8b193aeda..211d102cf6 100644
--- a/target/mips/tcg/micromips_translate.c.inc
+++ b/target/mips/tcg/micromips_translate.c.inc
@@ -977,20 +977,24 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
gen_reserved_instruction(ctx);
return;
}
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL);
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL |
+ ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd);
tcg_gen_movi_tl(t1, 4);
gen_op_addr_add(ctx, t0, t0, t1);
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL);
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL |
+ ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd + 1);
break;
case SWP:
gen_load_gpr(t1, rd);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+ ctx->default_tcg_memop_mask);
tcg_gen_movi_tl(t1, 4);
gen_op_addr_add(ctx, t0, t0, t1);
gen_load_gpr(t1, rd + 1);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+ ctx->default_tcg_memop_mask);
break;
#ifdef TARGET_MIPS64
case LDP:
@@ -998,20 +1002,24 @@ static void gen_ldst_pair(DisasContext *ctx, uint32_t opc, int rd,
gen_reserved_instruction(ctx);
return;
}
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ);
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
+ ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd);
tcg_gen_movi_tl(t1, 8);
gen_op_addr_add(ctx, t0, t0, t1);
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ);
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
+ ctx->default_tcg_memop_mask);
gen_store_gpr(t1, rd + 1);
break;
case SDP:
gen_load_gpr(t1, rd);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
+ ctx->default_tcg_memop_mask);
tcg_gen_movi_tl(t1, 8);
gen_op_addr_add(ctx, t0, t0, t1);
gen_load_gpr(t1, rd + 1);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUQ |
+ ctx->default_tcg_memop_mask);
break;
#endif
}
diff --git a/target/mips/tcg/mips16e_translate.c.inc b/target/mips/tcg/mips16e_translate.c.inc
index 602f5f0c02..5cffe0e412 100644
--- a/target/mips/tcg/mips16e_translate.c.inc
+++ b/target/mips/tcg/mips16e_translate.c.inc
@@ -172,22 +172,26 @@ static void gen_mips16_save(DisasContext *ctx,
case 4:
gen_base_offset_addr(ctx, t0, 29, 12);
gen_load_gpr(t1, 7);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+ ctx->default_tcg_memop_mask);
/* Fall through */
case 3:
gen_base_offset_addr(ctx, t0, 29, 8);
gen_load_gpr(t1, 6);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+ ctx->default_tcg_memop_mask);
/* Fall through */
case 2:
gen_base_offset_addr(ctx, t0, 29, 4);
gen_load_gpr(t1, 5);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+ ctx->default_tcg_memop_mask);
/* Fall through */
case 1:
gen_base_offset_addr(ctx, t0, 29, 0);
gen_load_gpr(t1, 4);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL |
+ ctx->default_tcg_memop_mask);
}
gen_load_gpr(t0, 29);
@@ -196,7 +200,8 @@ static void gen_mips16_save(DisasContext *ctx,
tcg_gen_movi_tl(t2, -4); \
gen_op_addr_add(ctx, t0, t0, t2); \
gen_load_gpr(t1, reg); \
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); \
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | \
+ ctx->default_tcg_memop_mask); \
} while (0)
if (do_ra) {
@@ -298,7 +303,8 @@ static void gen_mips16_restore(DisasContext *ctx,
#define DECR_AND_LOAD(reg) do { \
tcg_gen_movi_tl(t2, -4); \
gen_op_addr_add(ctx, t0, t0, t2); \
- tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); \
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL | \
+ ctx->default_tcg_memop_mask); \
gen_store_gpr(t1, reg); \
} while (0)
diff --git a/target/mips/tcg/nanomips_translate.c.inc b/target/mips/tcg/nanomips_translate.c.inc
index e08343414c..b96dcd2ae9 100644
--- a/target/mips/tcg/nanomips_translate.c.inc
+++ b/target/mips/tcg/nanomips_translate.c.inc
@@ -2641,52 +2641,49 @@ static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
switch (extract32(ctx->opcode, 7, 4)) {
case NM_LBX:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
- MO_SB);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SB);
gen_store_gpr(t0, rd);
break;
case NM_LHX:
/*case NM_LHXS:*/
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
- MO_TESW);
+ MO_TESW | ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rd);
break;
case NM_LWX:
/*case NM_LWXS:*/
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
- MO_TESL);
+ MO_TESL | ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rd);
break;
case NM_LBUX:
- tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
- MO_UB);
+ tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_UB);
gen_store_gpr(t0, rd);
break;
case NM_LHUX:
/*case NM_LHUXS:*/
tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
- MO_TEUW);
+ MO_TEUW | ctx->default_tcg_memop_mask);
gen_store_gpr(t0, rd);
break;
case NM_SBX:
check_nms(ctx);
gen_load_gpr(t1, rd);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
- MO_8);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_8);
break;
case NM_SHX:
/*case NM_SHXS:*/
check_nms(ctx);
gen_load_gpr(t1, rd);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
- MO_TEUW);
+ MO_TEUW | ctx->default_tcg_memop_mask);
break;
case NM_SWX:
/*case NM_SWXS:*/
check_nms(ctx);
gen_load_gpr(t1, rd);
tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
- MO_TEUL);
+ MO_TEUL | ctx->default_tcg_memop_mask);
break;
case NM_LWC1X:
/*case NM_LWC1XS:*/
@@ -3739,7 +3736,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
addr_off);
tcg_gen_movi_tl(t0, addr);
- tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx, MO_TESL);
+ tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx,
+ MO_TESL | ctx->default_tcg_memop_mask);
}
break;
case NM_SWPC48:
@@ -3755,7 +3753,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
tcg_gen_movi_tl(t0, addr);
gen_load_gpr(t1, rt);
- tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL);
+ tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
+ MO_TEUL | ctx->default_tcg_memop_mask);
}
break;
default:
--
2.34.1
next prev parent reply other threads:[~2023-05-11 8:17 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-11 8:03 [PULL 00/53] tcg patch queue Richard Henderson
2023-05-11 8:03 ` [PULL 01/53] target/m68k: Fix gen_load_fp for OS_LONG Richard Henderson
2023-05-11 8:03 ` [PULL 02/53] accel/tcg: Fix atomic_mmu_lookup for reads Richard Henderson
2023-05-11 8:04 ` [PULL 03/53] disas: Fix tabs and braces in disas.c Richard Henderson
2023-05-11 8:04 ` [PULL 04/53] disas: Move disas.c to disas/ Richard Henderson
2023-05-11 8:04 ` [PULL 05/53] disas: Remove target_ulong from the interface Richard Henderson
2023-05-11 8:04 ` [PULL 06/53] disas: Remove target-specific headers Richard Henderson
2023-05-11 8:04 ` [PULL 07/53] disas: Move softmmu specific code to separate file Richard Henderson
2023-05-11 8:04 ` [PULL 08/53] disas: Move disas.c into the target-independent source set Richard Henderson
2023-05-11 8:04 ` [PULL 09/53] cpu: expose qemu_cpu_list_lock for lock-guard use Richard Henderson
2023-05-11 8:04 ` [PULL 10/53] accel/tcg/tcg-accel-ops-rr: ensure fairness with icount Richard Henderson
2023-05-11 8:04 ` [PULL 11/53] tcg/i386: Introduce prepare_host_addr Richard Henderson
2023-05-11 8:04 ` [PULL 12/53] tcg/i386: Use indexed addressing for softmmu fast path Richard Henderson
2023-05-11 8:04 ` [PULL 13/53] tcg/aarch64: Introduce prepare_host_addr Richard Henderson
2023-05-11 8:04 ` [PULL 14/53] tcg/arm: " Richard Henderson
2023-05-11 8:04 ` [PULL 15/53] tcg/loongarch64: " Richard Henderson
2023-05-11 8:04 ` [PULL 16/53] tcg/mips: " Richard Henderson
2023-05-11 8:04 ` [PULL 17/53] tcg/ppc: " Richard Henderson
2023-05-11 8:04 ` [PULL 18/53] tcg/riscv: " Richard Henderson
2023-05-11 8:04 ` [PULL 19/53] tcg/s390x: " Richard Henderson
2023-05-11 8:04 ` [PULL 20/53] tcg: Add routines for calling slow-path helpers Richard Henderson
2023-05-11 8:04 ` [PULL 21/53] tcg/i386: Convert tcg_out_qemu_ld_slow_path Richard Henderson
2023-05-11 8:04 ` [PULL 22/53] tcg/i386: Convert tcg_out_qemu_st_slow_path Richard Henderson
2023-05-11 8:04 ` [PULL 23/53] tcg/aarch64: Convert tcg_out_qemu_{ld,st}_slow_path Richard Henderson
2023-05-11 8:04 ` [PULL 24/53] tcg/arm: " Richard Henderson
2023-05-11 8:04 ` [PULL 25/53] tcg/loongarch64: " Richard Henderson
2023-05-11 8:04 ` [PULL 26/53] tcg/mips: " Richard Henderson
2023-05-11 8:04 ` [PULL 27/53] tcg/ppc: " Richard Henderson
2023-05-11 8:04 ` [PULL 28/53] tcg/riscv: " Richard Henderson
2023-05-11 8:04 ` [PULL 29/53] tcg/s390x: " Richard Henderson
2023-05-11 8:04 ` [PULL 30/53] tcg/loongarch64: Simplify constraints on qemu_ld/st Richard Henderson
2023-05-11 8:04 ` [PULL 31/53] tcg/mips: Remove MO_BSWAP handling Richard Henderson
2023-05-11 8:04 ` [PULL 32/53] tcg/mips: Reorg tlb load within prepare_host_addr Richard Henderson
2023-05-11 8:04 ` [PULL 33/53] tcg/mips: Simplify constraints on qemu_ld/st Richard Henderson
2023-05-11 8:04 ` [PULL 34/53] tcg/ppc: Reorg tcg_out_tlb_read Richard Henderson
2023-05-11 8:04 ` [PULL 35/53] tcg/ppc: Adjust constraints on qemu_ld/st Richard Henderson
2023-05-11 8:04 ` [PULL 36/53] tcg/ppc: Remove unused constraints A, B, C, D Richard Henderson
2023-05-11 8:04 ` [PULL 37/53] tcg/ppc: Remove unused constraint J Richard Henderson
2023-05-11 8:04 ` [PULL 38/53] tcg/riscv: Simplify constraints on qemu_ld/st Richard Henderson
2023-05-11 8:04 ` [PULL 39/53] tcg/s390x: Use ALGFR in constructing softmmu host address Richard Henderson
2023-05-11 8:04 ` [PULL 40/53] tcg/s390x: Simplify constraints on qemu_ld/st Richard Henderson
2023-05-11 8:04 ` [PULL 41/53] target/mips: Add MO_ALIGN to gen_llwp, gen_scwp Richard Henderson
2023-05-11 8:04 ` Richard Henderson [this message]
2023-05-11 8:04 ` [PULL 43/53] target/mips: Use MO_ALIGN instead of 0 Richard Henderson
2023-05-11 8:04 ` [PULL 44/53] target/mips: Remove TARGET_ALIGNED_ONLY Richard Henderson
2023-05-11 8:04 ` [PULL 45/53] target/nios2: " Richard Henderson
2023-05-11 8:04 ` [PULL 46/53] target/sh4: Use MO_ALIGN where required Richard Henderson
2023-05-11 8:04 ` [PULL 47/53] target/sh4: Remove TARGET_ALIGNED_ONLY Richard Henderson
2023-05-11 8:04 ` [PULL 48/53] tcg: " Richard Henderson
2023-05-11 8:04 ` [PULL 49/53] accel/tcg: Add cpu_in_serial_context Richard Henderson
2023-05-11 8:04 ` [PULL 50/53] accel/tcg: Introduce tlb_read_idx Richard Henderson
2023-05-11 8:04 ` [PULL 51/53] accel/tcg: Reorg system mode load helpers Richard Henderson
2023-05-11 8:04 ` [PULL 52/53] accel/tcg: Reorg system mode store helpers Richard Henderson
2023-05-11 8:04 ` [PULL 53/53] target/loongarch: Do not include tcg-ldst.h Richard Henderson
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