From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PULL 48/53] tcg: Remove TARGET_ALIGNED_ONLY
Date: Thu, 11 May 2023 09:04:45 +0100 [thread overview]
Message-ID: <20230511080450.860923-49-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230511080450.860923-1-richard.henderson@linaro.org>
All uses have now been expunged.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/memop.h | 13 ++-----------
include/exec/poison.h | 1 -
tcg/tcg.c | 5 -----
3 files changed, 2 insertions(+), 17 deletions(-)
diff --git a/include/exec/memop.h b/include/exec/memop.h
index 25d027434a..07f5f88188 100644
--- a/include/exec/memop.h
+++ b/include/exec/memop.h
@@ -47,8 +47,6 @@ typedef enum MemOp {
* MO_UNALN accesses are never checked for alignment.
* MO_ALIGN accesses will result in a call to the CPU's
* do_unaligned_access hook if the guest address is not aligned.
- * The default depends on whether the target CPU defines
- * TARGET_ALIGNED_ONLY.
*
* Some architectures (e.g. ARMv8) need the address which is aligned
* to a size more than the size of the memory access.
@@ -65,21 +63,14 @@ typedef enum MemOp {
*/
MO_ASHIFT = 5,
MO_AMASK = 0x7 << MO_ASHIFT,
-#ifdef NEED_CPU_H
-#ifdef TARGET_ALIGNED_ONLY
- MO_ALIGN = 0,
- MO_UNALN = MO_AMASK,
-#else
- MO_ALIGN = MO_AMASK,
- MO_UNALN = 0,
-#endif
-#endif
+ MO_UNALN = 0,
MO_ALIGN_2 = 1 << MO_ASHIFT,
MO_ALIGN_4 = 2 << MO_ASHIFT,
MO_ALIGN_8 = 3 << MO_ASHIFT,
MO_ALIGN_16 = 4 << MO_ASHIFT,
MO_ALIGN_32 = 5 << MO_ASHIFT,
MO_ALIGN_64 = 6 << MO_ASHIFT,
+ MO_ALIGN = MO_AMASK,
/* Combinations of the above, for ease of use. */
MO_UB = MO_8,
diff --git a/include/exec/poison.h b/include/exec/poison.h
index 140daa4a85..256736e11a 100644
--- a/include/exec/poison.h
+++ b/include/exec/poison.h
@@ -35,7 +35,6 @@
#pragma GCC poison TARGET_TRICORE
#pragma GCC poison TARGET_XTENSA
-#pragma GCC poison TARGET_ALIGNED_ONLY
#pragma GCC poison TARGET_HAS_BFLT
#pragma GCC poison TARGET_NAME
#pragma GCC poison TARGET_SUPPORTS_MTTCG
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 88fe01f59f..1231c8ab4c 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -2185,13 +2185,8 @@ static const char * const ldst_name[] =
};
static const char * const alignment_name[(MO_AMASK >> MO_ASHIFT) + 1] = {
-#ifdef TARGET_ALIGNED_ONLY
[MO_UNALN >> MO_ASHIFT] = "un+",
- [MO_ALIGN >> MO_ASHIFT] = "",
-#else
- [MO_UNALN >> MO_ASHIFT] = "",
[MO_ALIGN >> MO_ASHIFT] = "al+",
-#endif
[MO_ALIGN_2 >> MO_ASHIFT] = "al2+",
[MO_ALIGN_4 >> MO_ASHIFT] = "al4+",
[MO_ALIGN_8 >> MO_ASHIFT] = "al8+",
--
2.34.1
next prev parent reply other threads:[~2023-05-11 8:12 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-11 8:03 [PULL 00/53] tcg patch queue Richard Henderson
2023-05-11 8:03 ` [PULL 01/53] target/m68k: Fix gen_load_fp for OS_LONG Richard Henderson
2023-05-11 8:03 ` [PULL 02/53] accel/tcg: Fix atomic_mmu_lookup for reads Richard Henderson
2023-05-11 8:04 ` [PULL 03/53] disas: Fix tabs and braces in disas.c Richard Henderson
2023-05-11 8:04 ` [PULL 04/53] disas: Move disas.c to disas/ Richard Henderson
2023-05-11 8:04 ` [PULL 05/53] disas: Remove target_ulong from the interface Richard Henderson
2023-05-11 8:04 ` [PULL 06/53] disas: Remove target-specific headers Richard Henderson
2023-05-11 8:04 ` [PULL 07/53] disas: Move softmmu specific code to separate file Richard Henderson
2023-05-11 8:04 ` [PULL 08/53] disas: Move disas.c into the target-independent source set Richard Henderson
2023-05-11 8:04 ` [PULL 09/53] cpu: expose qemu_cpu_list_lock for lock-guard use Richard Henderson
2023-05-11 8:04 ` [PULL 10/53] accel/tcg/tcg-accel-ops-rr: ensure fairness with icount Richard Henderson
2023-05-11 8:04 ` [PULL 11/53] tcg/i386: Introduce prepare_host_addr Richard Henderson
2023-05-11 8:04 ` [PULL 12/53] tcg/i386: Use indexed addressing for softmmu fast path Richard Henderson
2023-05-11 8:04 ` [PULL 13/53] tcg/aarch64: Introduce prepare_host_addr Richard Henderson
2023-05-11 8:04 ` [PULL 14/53] tcg/arm: " Richard Henderson
2023-05-11 8:04 ` [PULL 15/53] tcg/loongarch64: " Richard Henderson
2023-05-11 8:04 ` [PULL 16/53] tcg/mips: " Richard Henderson
2023-05-11 8:04 ` [PULL 17/53] tcg/ppc: " Richard Henderson
2023-05-11 8:04 ` [PULL 18/53] tcg/riscv: " Richard Henderson
2023-05-11 8:04 ` [PULL 19/53] tcg/s390x: " Richard Henderson
2023-05-11 8:04 ` [PULL 20/53] tcg: Add routines for calling slow-path helpers Richard Henderson
2023-05-11 8:04 ` [PULL 21/53] tcg/i386: Convert tcg_out_qemu_ld_slow_path Richard Henderson
2023-05-11 8:04 ` [PULL 22/53] tcg/i386: Convert tcg_out_qemu_st_slow_path Richard Henderson
2023-05-11 8:04 ` [PULL 23/53] tcg/aarch64: Convert tcg_out_qemu_{ld,st}_slow_path Richard Henderson
2023-05-11 8:04 ` [PULL 24/53] tcg/arm: " Richard Henderson
2023-05-11 8:04 ` [PULL 25/53] tcg/loongarch64: " Richard Henderson
2023-05-11 8:04 ` [PULL 26/53] tcg/mips: " Richard Henderson
2023-05-11 8:04 ` [PULL 27/53] tcg/ppc: " Richard Henderson
2023-05-11 8:04 ` [PULL 28/53] tcg/riscv: " Richard Henderson
2023-05-11 8:04 ` [PULL 29/53] tcg/s390x: " Richard Henderson
2023-05-11 8:04 ` [PULL 30/53] tcg/loongarch64: Simplify constraints on qemu_ld/st Richard Henderson
2023-05-11 8:04 ` [PULL 31/53] tcg/mips: Remove MO_BSWAP handling Richard Henderson
2023-05-11 8:04 ` [PULL 32/53] tcg/mips: Reorg tlb load within prepare_host_addr Richard Henderson
2023-05-11 8:04 ` [PULL 33/53] tcg/mips: Simplify constraints on qemu_ld/st Richard Henderson
2023-05-11 8:04 ` [PULL 34/53] tcg/ppc: Reorg tcg_out_tlb_read Richard Henderson
2023-05-11 8:04 ` [PULL 35/53] tcg/ppc: Adjust constraints on qemu_ld/st Richard Henderson
2023-05-11 8:04 ` [PULL 36/53] tcg/ppc: Remove unused constraints A, B, C, D Richard Henderson
2023-05-11 8:04 ` [PULL 37/53] tcg/ppc: Remove unused constraint J Richard Henderson
2023-05-11 8:04 ` [PULL 38/53] tcg/riscv: Simplify constraints on qemu_ld/st Richard Henderson
2023-05-11 8:04 ` [PULL 39/53] tcg/s390x: Use ALGFR in constructing softmmu host address Richard Henderson
2023-05-11 8:04 ` [PULL 40/53] tcg/s390x: Simplify constraints on qemu_ld/st Richard Henderson
2023-05-11 8:04 ` [PULL 41/53] target/mips: Add MO_ALIGN to gen_llwp, gen_scwp Richard Henderson
2023-05-11 8:04 ` [PULL 42/53] target/mips: Add missing default_tcg_memop_mask Richard Henderson
2023-05-11 8:04 ` [PULL 43/53] target/mips: Use MO_ALIGN instead of 0 Richard Henderson
2023-05-11 8:04 ` [PULL 44/53] target/mips: Remove TARGET_ALIGNED_ONLY Richard Henderson
2023-05-11 8:04 ` [PULL 45/53] target/nios2: " Richard Henderson
2023-05-11 8:04 ` [PULL 46/53] target/sh4: Use MO_ALIGN where required Richard Henderson
2023-05-11 8:04 ` [PULL 47/53] target/sh4: Remove TARGET_ALIGNED_ONLY Richard Henderson
2023-05-11 8:04 ` Richard Henderson [this message]
2023-05-11 8:04 ` [PULL 49/53] accel/tcg: Add cpu_in_serial_context Richard Henderson
2023-05-11 8:04 ` [PULL 50/53] accel/tcg: Introduce tlb_read_idx Richard Henderson
2023-05-11 8:04 ` [PULL 51/53] accel/tcg: Reorg system mode load helpers Richard Henderson
2023-05-11 8:04 ` [PULL 52/53] accel/tcg: Reorg system mode store helpers Richard Henderson
2023-05-11 8:04 ` [PULL 53/53] target/loongarch: Do not include tcg-ldst.h Richard Henderson
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