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[86.9.131.95]) by smtp.gmail.com with ESMTPSA id k15-20020a5d428f000000b003062d815fa6sm25573208wrq.85.2023.05.13.01.05.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 13 May 2023 01:05:39 -0700 (PDT) From: Stafford Horne To: QEMU Development Cc: Stafford Horne Subject: [PULL 0/3] OpenRISC FPU Updates for 8.1 Date: Sat, 13 May 2023 09:05:31 +0100 Message-Id: <20230513080534.580800-1-shorne@gmail.com> X-Mailer: git-send-email 2.39.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=shorne@gmail.com; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The following changes since commit c1eb2ddf0f8075faddc5f7c3d39feae3e8e9d6b4: Update version for v8.0.0 release (2023-04-19 17:27:13 +0100) are available in the Git repository at: https://github.com/stffrdhrn/qemu.git tags/or1k-pull-request-20230513 for you to fetch changes up to 874c52991e1fbe020812b4b15440b6875369aacf: target/openrisc: Setup FPU for detecting tininess before rounding (2023-05-11 15:40:28 +0100) ---------------------------------------------------------------- OpenRISC FPU Updates for 8.1 A few fixes and updates to bring OpenRISC inline with the latest architecture spec updates: - Allow FPCSR to be accessed in user mode - Select tininess detection before rounding - Fix FPE Exception PC value ---------------------------------------------------------------- Stafford Horne (3): target/openrisc: Allow fpcsr access in user mode target/openrisc: Set PC to cpu state on FPU exception target/openrisc: Setup FPU for detecting tininess before rounding target/openrisc/cpu.c | 4 +++ target/openrisc/fpu_helper.c | 13 ++++++-- target/openrisc/sys_helper.c | 45 ++++++++++++++++++++------- target/openrisc/translate.c | 72 ++++++++++++++++++++------------------------ 4 files changed, 81 insertions(+), 53 deletions(-)