From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-ppc@nongnu.org
Cc: Nicholas Piggin <npiggin@gmail.com>,
qemu-devel@nongnu.org,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH v3 2/9] target/ppc: Fix PMU MMCR0[PMCjCE] bit in hflags calculation
Date: Mon, 15 May 2023 19:26:48 +1000 [thread overview]
Message-ID: <20230515092655.171206-3-npiggin@gmail.com> (raw)
In-Reply-To: <20230515092655.171206-1-npiggin@gmail.com>
A store to MMCR0 with PMCjCE=1 fails to update hflags correctly and
results in hflags mismatch:
qemu: fatal: TCG hflags mismatch (current:0x2408003d rebuilt:0x240a003d)
This can be reproduced by running perf on a recent machine.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
Since v2: new patch.
target/ppc/power8-pmu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c
index 64a64865d7..29e0012ed6 100644
--- a/target/ppc/power8-pmu.c
+++ b/target/ppc/power8-pmu.c
@@ -236,14 +236,16 @@ void helper_store_mmcr0(CPUPPCState *env, target_ulong value)
{
bool hflags_pmcc0 = (value & MMCR0_PMCC0) != 0;
bool hflags_pmcc1 = (value & MMCR0_PMCC1) != 0;
+ bool hflags_pmcjce = (value & MMCR0_PMCjCE) != 0;
pmu_update_cycles(env);
env->spr[SPR_POWER_MMCR0] = value;
- /* MMCR0 writes can change HFLAGS_PMCC[01] and HFLAGS_INSN_CNT */
+ /* MMCR0 writes can change HFLAGS_PMCC[01], PMCjCE, and HFLAGS_INSN_CNT */
env->hflags = deposit32(env->hflags, HFLAGS_PMCC0, 1, hflags_pmcc0);
env->hflags = deposit32(env->hflags, HFLAGS_PMCC1, 1, hflags_pmcc1);
+ env->hflags = deposit32(env->hflags, HFLAGS_PMCJCE, 1, hflags_pmcjce);
pmu_update_summaries(env);
--
2.40.1
next prev parent reply other threads:[~2023-05-15 9:28 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-15 9:26 [PATCH v3 0/9] target/ppc: Assorted ppc target fixes Nicholas Piggin
2023-05-15 9:26 ` [PATCH v3 1/9] target/ppc: Fix width of some 32-bit SPRs Nicholas Piggin
2023-05-15 10:14 ` Harsh Prateek Bora
2023-05-15 11:14 ` Nicholas Piggin
2023-05-15 11:43 ` Harsh Prateek Bora
2023-05-15 12:03 ` Mark Cave-Ayland
2023-05-15 12:51 ` Nicholas Piggin
2023-05-15 15:19 ` Nicholas Piggin
2023-05-16 7:02 ` Mark Cave-Ayland
2023-05-16 9:39 ` Nicholas Piggin
2023-05-15 9:26 ` Nicholas Piggin [this message]
2023-05-16 9:32 ` [PATCH v3 2/9] target/ppc: Fix PMU MMCR0[PMCjCE] bit in hflags calculation Daniel Henrique Barboza
2023-05-16 10:44 ` Nicholas Piggin
2023-05-16 11:07 ` Daniel Henrique Barboza
2023-05-15 9:26 ` [PATCH v3 3/9] target/ppc: Fix instruction loading endianness in alignment interrupt Nicholas Piggin
2023-05-16 15:46 ` Daniel Henrique Barboza
2023-05-15 9:26 ` [PATCH v3 4/9] target/ppc: Alignment faults do not set DSISR in ISA v3.0 onward Nicholas Piggin
2023-05-15 9:26 ` [PATCH v3 5/9] target/ppc: Change partition-scope translate interface Nicholas Piggin
2023-05-15 9:26 ` [PATCH v3 6/9] target/ppc: Add SRR1 prefix indication to interrupt handlers Nicholas Piggin
2023-05-15 9:26 ` [PATCH v3 7/9] target/ppc: Implement HEIR SPR Nicholas Piggin
2023-05-15 9:26 ` [PATCH v3 8/9] target/ppc: Add ISA v3.1 LEV indication in SRR1 for system call interrupts Nicholas Piggin
2023-05-15 9:26 ` [PATCH v3 9/9] target/ppc: Better CTRL SPR implementation Nicholas Piggin
2023-05-27 18:05 ` [PATCH v3 0/9] target/ppc: Assorted ppc target fixes Daniel Henrique Barboza
2023-05-29 1:47 ` Nicholas Piggin
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