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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org,
	Peter Maydell <peter.maydell@linaro.org>
Subject: [PATCH v5 15/54] tcg/i386: Use full load/store helpers in user-only mode
Date: Mon, 15 May 2023 07:32:34 -0700	[thread overview]
Message-ID: <20230515143313.734053-16-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230515143313.734053-1-richard.henderson@linaro.org>

Instead of using helper_unaligned_{ld,st}, use the full load/store helpers.
This will allow the fast path to increase alignment to implement atomicity
while not immediately raising an alignment exception.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/i386/tcg-target.c.inc | 52 +++------------------------------------
 1 file changed, 4 insertions(+), 48 deletions(-)

diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 911123cfa8..21553f3c39 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -1776,7 +1776,6 @@ typedef struct {
     int seg;
 } HostAddress;
 
-#if defined(CONFIG_SOFTMMU)
 /*
  * Because i686 has no register parameters and because x86_64 has xchg
  * to handle addr/data register overlap, we have placed all input arguments
@@ -1812,7 +1811,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
 
     /* resolve label address */
     tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4);
-    if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
+    if (label_ptr[1]) {
         tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4);
     }
 
@@ -1834,7 +1833,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
 
     /* resolve label address */
     tcg_patch32(label_ptr[0], s->code_ptr - label_ptr[0] - 4);
-    if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
+    if (label_ptr[1]) {
         tcg_patch32(label_ptr[1], s->code_ptr - label_ptr[1] - 4);
     }
 
@@ -1844,51 +1843,8 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
     tcg_out_jmp(s, l->raddr);
     return true;
 }
-#else
-static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l)
-{
-    /* resolve label address */
-    tcg_patch32(l->label_ptr[0], s->code_ptr - l->label_ptr[0] - 4);
-
-    if (TCG_TARGET_REG_BITS == 32) {
-        int ofs = 0;
-
-        tcg_out_st(s, TCG_TYPE_PTR, TCG_AREG0, TCG_REG_ESP, ofs);
-        ofs += 4;
-
-        tcg_out_st(s, TCG_TYPE_I32, l->addrlo_reg, TCG_REG_ESP, ofs);
-        ofs += 4;
-        if (TARGET_LONG_BITS == 64) {
-            tcg_out_st(s, TCG_TYPE_I32, l->addrhi_reg, TCG_REG_ESP, ofs);
-            ofs += 4;
-        }
-
-        tcg_out_pushi(s, (uintptr_t)l->raddr);
-    } else {
-        tcg_out_mov(s, TCG_TYPE_TL, tcg_target_call_iarg_regs[1],
-                    l->addrlo_reg);
-        tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
-
-        tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RAX, (uintptr_t)l->raddr);
-        tcg_out_push(s, TCG_REG_RAX);
-    }
-
-    /* "Tail call" to the helper, with the return address back inline. */
-    tcg_out_jmp(s, (const void *)(l->is_ld ? helper_unaligned_ld
-                                  : helper_unaligned_st));
-    return true;
-}
-
-static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
-{
-    return tcg_out_fail_alignment(s, l);
-}
-
-static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
-{
-    return tcg_out_fail_alignment(s, l);
-}
 
+#ifndef CONFIG_SOFTMMU
 static HostAddress x86_guest_base = {
     .index = -1
 };
@@ -1920,7 +1876,7 @@ static inline int setup_guest_base_seg(void)
     return 0;
 }
 #endif /* setup_guest_base_seg */
-#endif /* SOFTMMU */
+#endif /* !SOFTMMU */
 
 /*
  * For softmmu, perform the TLB load and compare.
-- 
2.34.1



  parent reply	other threads:[~2023-05-15 14:44 UTC|newest]

Thread overview: 86+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-15 14:32 [PATCH v5 00/54] tcg: Improve atomicity support Richard Henderson
2023-05-15 14:32 ` [PATCH v5 01/54] include/exec/memop: Add MO_ATOM_* Richard Henderson
2023-05-15 16:32   ` Peter Maydell
2023-05-15 14:32 ` [PATCH v5 02/54] accel/tcg: Honor atomicity of loads Richard Henderson
2023-05-15 16:43   ` Peter Maydell
2023-05-15 23:24     ` Richard Henderson
2023-05-16 13:13   ` Peter Maydell
2023-05-16 13:48     ` Richard Henderson
2023-05-15 14:32 ` [PATCH v5 03/54] accel/tcg: Honor atomicity of stores Richard Henderson
2023-05-15 16:48   ` Peter Maydell
2023-05-15 14:32 ` [PATCH v5 04/54] tcg: Unify helper_{be,le}_{ld,st}* Richard Henderson
2023-05-15 14:32 ` [PATCH v5 05/54] accel/tcg: Implement helper_{ld, st}*_mmu for user-only Richard Henderson
2023-05-15 14:32 ` [PATCH v5 06/54] tcg/tci: Use helper_{ld,st}*_mmu " Richard Henderson
2023-05-15 14:32 ` [PATCH v5 07/54] tcg: Add 128-bit guest memory primitives Richard Henderson
2023-05-15 16:54   ` Peter Maydell
2023-05-15 14:32 ` [PATCH v5 08/54] meson: Detect atomic128 support with optimization Richard Henderson
2023-05-15 14:32 ` [PATCH v5 09/54] tcg/i386: Add have_atomic16 Richard Henderson
2023-05-15 16:56   ` Peter Maydell
2023-05-15 14:32 ` [PATCH v5 10/54] accel/tcg: Use have_atomic16 in ldst_atomicity.c.inc Richard Henderson
2023-05-16 10:38   ` Peter Maydell
2023-05-16 13:50     ` Richard Henderson
2023-05-15 14:32 ` [PATCH v5 11/54] accel/tcg: Add aarch64 specific support in ldst_atomicity Richard Henderson
2023-05-16 13:29   ` Peter Maydell
2023-05-16 13:51     ` Richard Henderson
2023-05-16 13:56       ` Peter Maydell
2023-05-16 14:04         ` Richard Henderson
2023-05-15 14:32 ` [PATCH v5 12/54] tcg/aarch64: Detect have_lse, have_lse2 for linux Richard Henderson
2023-05-15 14:32 ` [PATCH v5 13/54] tcg/aarch64: Detect have_lse, have_lse2 for darwin Richard Henderson
2023-05-15 14:32 ` [PATCH v5 14/54] accel/tcg: Add have_lse2 support in ldst_atomicity Richard Henderson
2023-05-16 13:16   ` Peter Maydell
2023-05-15 14:32 ` Richard Henderson [this message]
2023-05-15 14:32 ` [PATCH v5 16/54] tcg/aarch64: Use full load/store helpers in user-only mode Richard Henderson
2023-05-15 14:32 ` [PATCH v5 17/54] tcg/ppc: " Richard Henderson
2023-05-15 14:32 ` [PATCH v5 18/54] tcg/loongarch64: " Richard Henderson
2023-05-15 14:32 ` [PATCH v5 19/54] tcg/riscv: " Richard Henderson
2023-05-15 14:32 ` [PATCH v5 20/54] tcg/arm: Adjust constraints on qemu_ld/st Richard Henderson
2023-05-15 16:58   ` Peter Maydell
2023-05-15 14:32 ` [PATCH v5 21/54] tcg/arm: Use full load/store helpers in user-only mode Richard Henderson
2023-05-15 14:32 ` [PATCH v5 22/54] tcg/mips: " Richard Henderson
2023-05-15 14:32 ` [PATCH v5 23/54] tcg/s390x: " Richard Henderson
2023-05-15 14:32 ` [PATCH v5 24/54] tcg/sparc64: Allocate %g2 as a third temporary Richard Henderson
2023-05-15 17:06   ` Peter Maydell
2023-05-15 14:32 ` [PATCH v5 25/54] tcg/sparc64: Rename tcg_out_movi_imm13 to tcg_out_movi_s13 Richard Henderson
2023-05-15 17:07   ` Peter Maydell
2023-05-15 14:32 ` [PATCH v5 26/54] target/sparc64: Remove tcg_out_movi_s13 case from tcg_out_movi_imm32 Richard Henderson
2023-05-15 17:12   ` Peter Maydell
2023-05-15 14:32 ` [PATCH v5 27/54] tcg/sparc64: Rename tcg_out_movi_imm32 to tcg_out_movi_u32 Richard Henderson
2023-05-15 17:14   ` Peter Maydell
2023-05-15 14:32 ` [PATCH v5 28/54] tcg/sparc64: Split out tcg_out_movi_s32 Richard Henderson
2023-05-15 14:32 ` [PATCH v5 29/54] tcg/sparc64: Use standard slow path for softmmu Richard Henderson
2023-05-16 10:53   ` Peter Maydell
2023-05-15 14:32 ` [PATCH v5 30/54] accel/tcg: Remove helper_unaligned_{ld,st} Richard Henderson
2023-05-15 14:32 ` [PATCH v5 31/54] tcg/loongarch64: Check the host supports unaligned accesses Richard Henderson
2023-05-16  9:44   ` Peter Maydell
2023-05-15 14:32 ` [PATCH v5 32/54] tcg/loongarch64: Support softmmu " Richard Henderson
2023-05-15 14:32 ` [PATCH v5 33/54] tcg/riscv: " Richard Henderson
2023-05-15 14:32 ` [PATCH v5 34/54] tcg: Introduce tcg_target_has_memory_bswap Richard Henderson
2023-05-15 14:32 ` [PATCH v5 35/54] tcg: Add INDEX_op_qemu_{ld,st}_i128 Richard Henderson
2023-05-15 14:32 ` [PATCH v5 36/54] tcg: Introduce tcg_out_movext3 Richard Henderson
2023-05-16 10:03   ` Peter Maydell
2023-05-16 13:56     ` Richard Henderson
2023-05-15 14:32 ` [PATCH v5 37/54] tcg: Merge tcg_out_helper_load_regs into caller Richard Henderson
2023-05-16 10:05   ` Peter Maydell
2023-05-15 14:32 ` [PATCH v5 38/54] tcg: Support TCG_TYPE_I128 in tcg_out_{ld, st}_helper_{args, ret} Richard Henderson
2023-05-15 14:32 ` [PATCH v5 39/54] tcg: Introduce atom_and_align_for_opc Richard Henderson
2023-05-16 10:08   ` Peter Maydell
2023-05-15 14:32 ` [PATCH v5 40/54] tcg/i386: Use atom_and_align_for_opc Richard Henderson
2023-05-16 10:11   ` Peter Maydell
2023-05-15 14:33 ` [PATCH v5 41/54] tcg/aarch64: " Richard Henderson
2023-05-15 14:33 ` [PATCH v5 42/54] tcg/arm: " Richard Henderson
2023-05-15 14:33 ` [PATCH v5 43/54] tcg/loongarch64: " Richard Henderson
2023-05-15 14:33 ` [PATCH v5 44/54] tcg/mips: " Richard Henderson
2023-05-15 14:33 ` [PATCH v5 45/54] tcg/ppc: " Richard Henderson
2023-05-16 10:12   ` Peter Maydell
2023-05-15 14:33 ` [PATCH v5 46/54] tcg/riscv: " Richard Henderson
2023-05-16 10:14   ` Peter Maydell
2023-05-15 14:33 ` [PATCH v5 47/54] tcg/s390x: " Richard Henderson
2023-05-15 14:33 ` [PATCH v5 48/54] tcg/sparc64: " Richard Henderson
2023-05-16 10:19   ` Peter Maydell
2023-05-15 14:33 ` [PATCH v5 49/54] tcg/i386: Honor 64-bit atomicity in 32-bit mode Richard Henderson
2023-05-15 14:33 ` [PATCH v5 50/54] tcg/i386: Support 128-bit load/store with have_atomic16 Richard Henderson
2023-05-15 14:33 ` [PATCH v5 51/54] tcg/aarch64: Rename temporaries Richard Henderson
2023-05-15 14:33 ` [PATCH v5 52/54] tcg/aarch64: Support 128-bit load/store Richard Henderson
2023-05-15 14:33 ` [PATCH v5 53/54] tcg/ppc: " Richard Henderson
2023-05-15 14:33 ` [PATCH v5 54/54] tcg/s390x: " Richard Henderson
2023-05-16 13:40   ` Peter Maydell

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