From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org,
Peter Maydell <peter.maydell@linaro.org>
Subject: [PATCH v5 08/54] meson: Detect atomic128 support with optimization
Date: Mon, 15 May 2023 07:32:27 -0700 [thread overview]
Message-ID: <20230515143313.734053-9-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230515143313.734053-1-richard.henderson@linaro.org>
There is an edge condition prior to gcc13 for which optimization
is required to generate 16-byte atomic sequences. Detect this.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
meson.build | 52 ++++++++++++++++++++++------------
accel/tcg/ldst_atomicity.c.inc | 29 ++++++++++++++++---
2 files changed, 59 insertions(+), 22 deletions(-)
diff --git a/meson.build b/meson.build
index d3cf48960b..61de8199cb 100644
--- a/meson.build
+++ b/meson.build
@@ -2249,23 +2249,21 @@ config_host_data.set('HAVE_BROKEN_SIZE_MAX', not cc.compiles('''
return printf("%zu", SIZE_MAX);
}''', args: ['-Werror']))
-atomic_test = '''
+# See if 64-bit atomic operations are supported.
+# Note that without __atomic builtins, we can only
+# assume atomic loads/stores max at pointer size.
+config_host_data.set('CONFIG_ATOMIC64', cc.links('''
#include <stdint.h>
int main(void)
{
- @0@ x = 0, y = 0;
+ uint64_t x = 0, y = 0;
y = __atomic_load_n(&x, __ATOMIC_RELAXED);
__atomic_store_n(&x, y, __ATOMIC_RELAXED);
__atomic_compare_exchange_n(&x, &y, x, 0, __ATOMIC_RELAXED, __ATOMIC_RELAXED);
__atomic_exchange_n(&x, y, __ATOMIC_RELAXED);
__atomic_fetch_add(&x, y, __ATOMIC_RELAXED);
return 0;
- }'''
-
-# See if 64-bit atomic operations are supported.
-# Note that without __atomic builtins, we can only
-# assume atomic loads/stores max at pointer size.
-config_host_data.set('CONFIG_ATOMIC64', cc.links(atomic_test.format('uint64_t')))
+ }'''))
has_int128 = cc.links('''
__int128_t a;
@@ -2283,21 +2281,39 @@ if has_int128
# "do we have 128-bit atomics which are handled inline and specifically not
# via libatomic". The reason we can't use libatomic is documented in the
# comment starting "GCC is a house divided" in include/qemu/atomic128.h.
- has_atomic128 = cc.links(atomic_test.format('unsigned __int128'))
+ # We only care about these operations on 16-byte aligned pointers, so
+ # force 16-byte alignment of the pointer, which may be greater than
+ # __alignof(unsigned __int128) for the host.
+ atomic_test_128 = '''
+ int main(int ac, char **av) {
+ unsigned __int128 *p = __builtin_assume_aligned(av[ac - 1], sizeof(16));
+ p[1] = __atomic_load_n(&p[0], __ATOMIC_RELAXED);
+ __atomic_store_n(&p[2], p[3], __ATOMIC_RELAXED);
+ __atomic_compare_exchange_n(&p[4], &p[5], p[6], 0, __ATOMIC_RELAXED, __ATOMIC_RELAXED);
+ return 0;
+ }'''
+ has_atomic128 = cc.links(atomic_test_128)
config_host_data.set('CONFIG_ATOMIC128', has_atomic128)
if not has_atomic128
- has_cmpxchg128 = cc.links('''
- int main(void)
- {
- unsigned __int128 x = 0, y = 0;
- __sync_val_compare_and_swap_16(&x, y, x);
- return 0;
- }
- ''')
+ # Even with __builtin_assume_aligned, the above test may have failed
+ # without optimization enabled. Try again with optimizations locally
+ # enabled for the function. See
+ # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107389
+ has_atomic128_opt = cc.links('__attribute__((optimize("O1")))' + atomic_test_128)
+ config_host_data.set('CONFIG_ATOMIC128_OPT', has_atomic128_opt)
- config_host_data.set('CONFIG_CMPXCHG128', has_cmpxchg128)
+ if not has_atomic128_opt
+ config_host_data.set('CONFIG_CMPXCHG128', cc.links('''
+ int main(void)
+ {
+ unsigned __int128 x = 0, y = 0;
+ __sync_val_compare_and_swap_16(&x, y, x);
+ return 0;
+ }
+ '''))
+ endif
endif
endif
diff --git a/accel/tcg/ldst_atomicity.c.inc b/accel/tcg/ldst_atomicity.c.inc
index 5cad4f4857..dd387c9bdd 100644
--- a/accel/tcg/ldst_atomicity.c.inc
+++ b/accel/tcg/ldst_atomicity.c.inc
@@ -16,6 +16,23 @@
#endif
#define HAVE_al8_fast (ATOMIC_REG_SIZE >= 8)
+/*
+ * If __alignof(unsigned __int128) < 16, GCC may refuse to inline atomics
+ * that are supported by the host, e.g. s390x. We can force the pointer to
+ * have our known alignment with __builtin_assume_aligned, however prior to
+ * GCC 13 that was only reliable with optimization enabled. See
+ * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107389
+ */
+#if defined(CONFIG_ATOMIC128_OPT)
+# if !defined(__OPTIMIZE__)
+# define ATTRIBUTE_ATOMIC128_OPT __attribute__((optimize("O1")))
+# endif
+# define CONFIG_ATOMIC128
+#endif
+#ifndef ATTRIBUTE_ATOMIC128_OPT
+# define ATTRIBUTE_ATOMIC128_OPT
+#endif
+
#if defined(CONFIG_ATOMIC128)
# define HAVE_al16_fast true
#else
@@ -152,7 +169,8 @@ static inline uint64_t load_atomic8(void *pv)
*
* Atomically load 16 aligned bytes from @pv.
*/
-static inline Int128 load_atomic16(void *pv)
+static inline Int128 ATTRIBUTE_ATOMIC128_OPT
+load_atomic16(void *pv)
{
#ifdef CONFIG_ATOMIC128
__uint128_t *p = __builtin_assume_aligned(pv, 16);
@@ -356,7 +374,8 @@ static uint64_t load_atom_extract_al16_or_exit(CPUArchState *env, uintptr_t ra,
* cross an 16-byte boundary then the access must be 16-byte atomic,
* otherwise the access must be 8-byte atomic.
*/
-static inline uint64_t load_atom_extract_al16_or_al8(void *pv, int s)
+static inline uint64_t ATTRIBUTE_ATOMIC128_OPT
+load_atom_extract_al16_or_al8(void *pv, int s)
{
#if defined(CONFIG_ATOMIC128)
uintptr_t pi = (uintptr_t)pv;
@@ -692,7 +711,8 @@ static inline void store_atomic8(void *pv, uint64_t val)
*
* Atomically store 16 aligned bytes to @pv.
*/
-static inline void store_atomic16(void *pv, Int128Alias val)
+static inline void ATTRIBUTE_ATOMIC128_OPT
+store_atomic16(void *pv, Int128Alias val)
{
#if defined(CONFIG_ATOMIC128)
__uint128_t *pu = __builtin_assume_aligned(pv, 16);
@@ -790,7 +810,8 @@ static void store_atom_insert_al8(uint64_t *p, uint64_t val, uint64_t msk)
*
* Atomically store @val to @p masked by @msk.
*/
-static void store_atom_insert_al16(Int128 *ps, Int128Alias val, Int128Alias msk)
+static void ATTRIBUTE_ATOMIC128_OPT
+store_atom_insert_al16(Int128 *ps, Int128Alias val, Int128Alias msk)
{
#if defined(CONFIG_ATOMIC128)
__uint128_t *pu, old, new;
--
2.34.1
next prev parent reply other threads:[~2023-05-15 14:43 UTC|newest]
Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-15 14:32 [PATCH v5 00/54] tcg: Improve atomicity support Richard Henderson
2023-05-15 14:32 ` [PATCH v5 01/54] include/exec/memop: Add MO_ATOM_* Richard Henderson
2023-05-15 16:32 ` Peter Maydell
2023-05-15 14:32 ` [PATCH v5 02/54] accel/tcg: Honor atomicity of loads Richard Henderson
2023-05-15 16:43 ` Peter Maydell
2023-05-15 23:24 ` Richard Henderson
2023-05-16 13:13 ` Peter Maydell
2023-05-16 13:48 ` Richard Henderson
2023-05-15 14:32 ` [PATCH v5 03/54] accel/tcg: Honor atomicity of stores Richard Henderson
2023-05-15 16:48 ` Peter Maydell
2023-05-15 14:32 ` [PATCH v5 04/54] tcg: Unify helper_{be,le}_{ld,st}* Richard Henderson
2023-05-15 14:32 ` [PATCH v5 05/54] accel/tcg: Implement helper_{ld, st}*_mmu for user-only Richard Henderson
2023-05-15 14:32 ` [PATCH v5 06/54] tcg/tci: Use helper_{ld,st}*_mmu " Richard Henderson
2023-05-15 14:32 ` [PATCH v5 07/54] tcg: Add 128-bit guest memory primitives Richard Henderson
2023-05-15 16:54 ` Peter Maydell
2023-05-15 14:32 ` Richard Henderson [this message]
2023-05-15 14:32 ` [PATCH v5 09/54] tcg/i386: Add have_atomic16 Richard Henderson
2023-05-15 16:56 ` Peter Maydell
2023-05-15 14:32 ` [PATCH v5 10/54] accel/tcg: Use have_atomic16 in ldst_atomicity.c.inc Richard Henderson
2023-05-16 10:38 ` Peter Maydell
2023-05-16 13:50 ` Richard Henderson
2023-05-15 14:32 ` [PATCH v5 11/54] accel/tcg: Add aarch64 specific support in ldst_atomicity Richard Henderson
2023-05-16 13:29 ` Peter Maydell
2023-05-16 13:51 ` Richard Henderson
2023-05-16 13:56 ` Peter Maydell
2023-05-16 14:04 ` Richard Henderson
2023-05-15 14:32 ` [PATCH v5 12/54] tcg/aarch64: Detect have_lse, have_lse2 for linux Richard Henderson
2023-05-15 14:32 ` [PATCH v5 13/54] tcg/aarch64: Detect have_lse, have_lse2 for darwin Richard Henderson
2023-05-15 14:32 ` [PATCH v5 14/54] accel/tcg: Add have_lse2 support in ldst_atomicity Richard Henderson
2023-05-16 13:16 ` Peter Maydell
2023-05-15 14:32 ` [PATCH v5 15/54] tcg/i386: Use full load/store helpers in user-only mode Richard Henderson
2023-05-15 14:32 ` [PATCH v5 16/54] tcg/aarch64: " Richard Henderson
2023-05-15 14:32 ` [PATCH v5 17/54] tcg/ppc: " Richard Henderson
2023-05-15 14:32 ` [PATCH v5 18/54] tcg/loongarch64: " Richard Henderson
2023-05-15 14:32 ` [PATCH v5 19/54] tcg/riscv: " Richard Henderson
2023-05-15 14:32 ` [PATCH v5 20/54] tcg/arm: Adjust constraints on qemu_ld/st Richard Henderson
2023-05-15 16:58 ` Peter Maydell
2023-05-15 14:32 ` [PATCH v5 21/54] tcg/arm: Use full load/store helpers in user-only mode Richard Henderson
2023-05-15 14:32 ` [PATCH v5 22/54] tcg/mips: " Richard Henderson
2023-05-15 14:32 ` [PATCH v5 23/54] tcg/s390x: " Richard Henderson
2023-05-15 14:32 ` [PATCH v5 24/54] tcg/sparc64: Allocate %g2 as a third temporary Richard Henderson
2023-05-15 17:06 ` Peter Maydell
2023-05-15 14:32 ` [PATCH v5 25/54] tcg/sparc64: Rename tcg_out_movi_imm13 to tcg_out_movi_s13 Richard Henderson
2023-05-15 17:07 ` Peter Maydell
2023-05-15 14:32 ` [PATCH v5 26/54] target/sparc64: Remove tcg_out_movi_s13 case from tcg_out_movi_imm32 Richard Henderson
2023-05-15 17:12 ` Peter Maydell
2023-05-15 14:32 ` [PATCH v5 27/54] tcg/sparc64: Rename tcg_out_movi_imm32 to tcg_out_movi_u32 Richard Henderson
2023-05-15 17:14 ` Peter Maydell
2023-05-15 14:32 ` [PATCH v5 28/54] tcg/sparc64: Split out tcg_out_movi_s32 Richard Henderson
2023-05-15 14:32 ` [PATCH v5 29/54] tcg/sparc64: Use standard slow path for softmmu Richard Henderson
2023-05-16 10:53 ` Peter Maydell
2023-05-15 14:32 ` [PATCH v5 30/54] accel/tcg: Remove helper_unaligned_{ld,st} Richard Henderson
2023-05-15 14:32 ` [PATCH v5 31/54] tcg/loongarch64: Check the host supports unaligned accesses Richard Henderson
2023-05-16 9:44 ` Peter Maydell
2023-05-15 14:32 ` [PATCH v5 32/54] tcg/loongarch64: Support softmmu " Richard Henderson
2023-05-15 14:32 ` [PATCH v5 33/54] tcg/riscv: " Richard Henderson
2023-05-15 14:32 ` [PATCH v5 34/54] tcg: Introduce tcg_target_has_memory_bswap Richard Henderson
2023-05-15 14:32 ` [PATCH v5 35/54] tcg: Add INDEX_op_qemu_{ld,st}_i128 Richard Henderson
2023-05-15 14:32 ` [PATCH v5 36/54] tcg: Introduce tcg_out_movext3 Richard Henderson
2023-05-16 10:03 ` Peter Maydell
2023-05-16 13:56 ` Richard Henderson
2023-05-15 14:32 ` [PATCH v5 37/54] tcg: Merge tcg_out_helper_load_regs into caller Richard Henderson
2023-05-16 10:05 ` Peter Maydell
2023-05-15 14:32 ` [PATCH v5 38/54] tcg: Support TCG_TYPE_I128 in tcg_out_{ld, st}_helper_{args, ret} Richard Henderson
2023-05-15 14:32 ` [PATCH v5 39/54] tcg: Introduce atom_and_align_for_opc Richard Henderson
2023-05-16 10:08 ` Peter Maydell
2023-05-15 14:32 ` [PATCH v5 40/54] tcg/i386: Use atom_and_align_for_opc Richard Henderson
2023-05-16 10:11 ` Peter Maydell
2023-05-15 14:33 ` [PATCH v5 41/54] tcg/aarch64: " Richard Henderson
2023-05-15 14:33 ` [PATCH v5 42/54] tcg/arm: " Richard Henderson
2023-05-15 14:33 ` [PATCH v5 43/54] tcg/loongarch64: " Richard Henderson
2023-05-15 14:33 ` [PATCH v5 44/54] tcg/mips: " Richard Henderson
2023-05-15 14:33 ` [PATCH v5 45/54] tcg/ppc: " Richard Henderson
2023-05-16 10:12 ` Peter Maydell
2023-05-15 14:33 ` [PATCH v5 46/54] tcg/riscv: " Richard Henderson
2023-05-16 10:14 ` Peter Maydell
2023-05-15 14:33 ` [PATCH v5 47/54] tcg/s390x: " Richard Henderson
2023-05-15 14:33 ` [PATCH v5 48/54] tcg/sparc64: " Richard Henderson
2023-05-16 10:19 ` Peter Maydell
2023-05-15 14:33 ` [PATCH v5 49/54] tcg/i386: Honor 64-bit atomicity in 32-bit mode Richard Henderson
2023-05-15 14:33 ` [PATCH v5 50/54] tcg/i386: Support 128-bit load/store with have_atomic16 Richard Henderson
2023-05-15 14:33 ` [PATCH v5 51/54] tcg/aarch64: Rename temporaries Richard Henderson
2023-05-15 14:33 ` [PATCH v5 52/54] tcg/aarch64: Support 128-bit load/store Richard Henderson
2023-05-15 14:33 ` [PATCH v5 53/54] tcg/ppc: " Richard Henderson
2023-05-15 14:33 ` [PATCH v5 54/54] tcg/s390x: " Richard Henderson
2023-05-16 13:40 ` Peter Maydell
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