From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>
Subject: [PULL 34/80] tcg: Introduce tcg_out_movext3
Date: Tue, 16 May 2023 12:40:59 -0700 [thread overview]
Message-ID: <20230516194145.1749305-35-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230516194145.1749305-1-richard.henderson@linaro.org>
With x86_64 as host, we do not have any temporaries with which to
resolve cycles, but we do have xchg. As a side bonus, the set of
graphs that can be made with 3 nodes and all nodes conflicting is
small: two. We can solve the cycle with a single temp.
This is required for x86_64 to handle stores of i128: 1 address
register and 2 data registers.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg.c | 138 ++++++++++++++++++++++++++++++++++++++++++------------
1 file changed, 108 insertions(+), 30 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 44b8c700a7..5de9380c6b 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -532,6 +532,82 @@ static void tcg_out_movext2(TCGContext *s, const TCGMovExtend *i1,
tcg_out_movext1_new_src(s, i1, src1);
}
+/**
+ * tcg_out_movext3 -- move and extend three pair
+ * @s: tcg context
+ * @i1: first move description
+ * @i2: second move description
+ * @i3: third move description
+ * @scratch: temporary register, or -1 for none
+ *
+ * As tcg_out_movext, for all of @i1, @i2 and @i3, caring for overlap
+ * between the sources and destinations.
+ */
+
+static void tcg_out_movext3(TCGContext *s, const TCGMovExtend *i1,
+ const TCGMovExtend *i2, const TCGMovExtend *i3,
+ int scratch)
+{
+ TCGReg src1 = i1->src;
+ TCGReg src2 = i2->src;
+ TCGReg src3 = i3->src;
+
+ if (i1->dst != src2 && i1->dst != src3) {
+ tcg_out_movext1(s, i1);
+ tcg_out_movext2(s, i2, i3, scratch);
+ return;
+ }
+ if (i2->dst != src1 && i2->dst != src3) {
+ tcg_out_movext1(s, i2);
+ tcg_out_movext2(s, i1, i3, scratch);
+ return;
+ }
+ if (i3->dst != src1 && i3->dst != src2) {
+ tcg_out_movext1(s, i3);
+ tcg_out_movext2(s, i1, i2, scratch);
+ return;
+ }
+
+ /*
+ * There is a cycle. Since there are only 3 nodes, the cycle is
+ * either "clockwise" or "anti-clockwise", and can be solved with
+ * a single scratch or two xchg.
+ */
+ if (i1->dst == src2 && i2->dst == src3 && i3->dst == src1) {
+ /* "Clockwise" */
+ if (tcg_out_xchg(s, MAX(i1->src_type, i2->src_type), src1, src2)) {
+ tcg_out_xchg(s, MAX(i2->src_type, i3->src_type), src2, src3);
+ /* The data is now in the correct registers, now extend. */
+ tcg_out_movext1_new_src(s, i1, i1->dst);
+ tcg_out_movext1_new_src(s, i2, i2->dst);
+ tcg_out_movext1_new_src(s, i3, i3->dst);
+ } else {
+ tcg_debug_assert(scratch >= 0);
+ tcg_out_mov(s, i1->src_type, scratch, src1);
+ tcg_out_movext1(s, i3);
+ tcg_out_movext1(s, i2);
+ tcg_out_movext1_new_src(s, i1, scratch);
+ }
+ } else if (i1->dst == src3 && i2->dst == src1 && i3->dst == src2) {
+ /* "Anti-clockwise" */
+ if (tcg_out_xchg(s, MAX(i2->src_type, i3->src_type), src2, src3)) {
+ tcg_out_xchg(s, MAX(i1->src_type, i2->src_type), src1, src2);
+ /* The data is now in the correct registers, now extend. */
+ tcg_out_movext1_new_src(s, i1, i1->dst);
+ tcg_out_movext1_new_src(s, i2, i2->dst);
+ tcg_out_movext1_new_src(s, i3, i3->dst);
+ } else {
+ tcg_debug_assert(scratch >= 0);
+ tcg_out_mov(s, i1->src_type, scratch, src1);
+ tcg_out_movext1(s, i2);
+ tcg_out_movext1(s, i3);
+ tcg_out_movext1_new_src(s, i1, scratch);
+ }
+ } else {
+ g_assert_not_reached();
+ }
+}
+
#define C_PFX1(P, A) P##A
#define C_PFX2(P, A, B) P##A##_##B
#define C_PFX3(P, A, B, C) P##A##_##B##_##C
@@ -5151,46 +5227,48 @@ static int tcg_out_helper_stk_ofs(TCGType type, unsigned slot)
static void tcg_out_helper_load_regs(TCGContext *s,
unsigned nmov, TCGMovExtend *mov,
- unsigned ntmp, const int *tmp)
+ const TCGLdstHelperParam *parm)
{
+ TCGReg dst3;
+
switch (nmov) {
- default:
+ case 4:
/* The backend must have provided enough temps for the worst case. */
- tcg_debug_assert(ntmp + 1 >= nmov);
+ tcg_debug_assert(parm->ntmp >= 2);
- for (unsigned i = nmov - 1; i >= 2; --i) {
- TCGReg dst = mov[i].dst;
+ dst3 = mov[3].dst;
+ for (unsigned j = 0; j < 3; ++j) {
+ if (dst3 == mov[j].src) {
+ /*
+ * Conflict. Copy the source to a temporary, perform the
+ * remaining moves, then the extension from our scratch
+ * on the way out.
+ */
+ TCGReg scratch = parm->tmp[1];
- for (unsigned j = 0; j < i; ++j) {
- if (dst == mov[j].src) {
- /*
- * Conflict.
- * Copy the source to a temporary, recurse for the
- * remaining moves, perform the extension from our
- * scratch on the way out.
- */
- TCGReg scratch = tmp[--ntmp];
- tcg_out_mov(s, mov[i].src_type, scratch, mov[i].src);
- mov[i].src = scratch;
-
- tcg_out_helper_load_regs(s, i, mov, ntmp, tmp);
- tcg_out_movext1(s, &mov[i]);
- return;
- }
+ tcg_out_mov(s, mov[3].src_type, scratch, mov[3].src);
+ tcg_out_movext3(s, mov, mov + 1, mov + 2, parm->tmp[0]);
+ tcg_out_movext1_new_src(s, &mov[3], scratch);
+ break;
}
-
- /* No conflicts: perform this move and continue. */
- tcg_out_movext1(s, &mov[i]);
}
- /* fall through for the final two moves */
+ /* No conflicts: perform this move and continue. */
+ tcg_out_movext1(s, &mov[3]);
+ /* fall through */
+
+ case 3:
+ tcg_out_movext3(s, mov, mov + 1, mov + 2,
+ parm->ntmp ? parm->tmp[0] : -1);
+ break;
case 2:
- tcg_out_movext2(s, mov, mov + 1, ntmp ? tmp[0] : -1);
- return;
+ tcg_out_movext2(s, mov, mov + 1,
+ parm->ntmp ? parm->tmp[0] : -1);
+ break;
case 1:
tcg_out_movext1(s, mov);
- return;
- case 0:
+ break;
+ default:
g_assert_not_reached();
}
}
@@ -5237,7 +5315,7 @@ static void tcg_out_helper_load_slots(TCGContext *s,
for (i = 0; i < nmov; ++i) {
mov[i].dst = tcg_target_call_iarg_regs[mov[i].dst];
}
- tcg_out_helper_load_regs(s, nmov, mov, parm->ntmp, parm->tmp);
+ tcg_out_helper_load_regs(s, nmov, mov, parm);
}
static void tcg_out_helper_load_imm(TCGContext *s, unsigned slot,
--
2.34.1
next prev parent reply other threads:[~2023-05-16 19:44 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-16 19:40 [PULL 00/80] tcg patch queue Richard Henderson
2023-05-16 19:40 ` [PULL 01/80] tcg/i386: Set P_REXW in tcg_out_addi_ptr Richard Henderson
2023-05-16 19:40 ` [PULL 02/80] include/exec/memop: Add MO_ATOM_* Richard Henderson
2023-05-16 19:40 ` [PULL 03/80] accel/tcg: Honor atomicity of loads Richard Henderson
2023-05-16 19:40 ` [PULL 04/80] accel/tcg: Honor atomicity of stores Richard Henderson
2023-05-16 19:40 ` [PULL 05/80] tcg: Unify helper_{be,le}_{ld,st}* Richard Henderson
2023-05-16 19:40 ` [PULL 06/80] accel/tcg: Implement helper_{ld,st}*_mmu for user-only Richard Henderson
2023-05-16 19:40 ` [PULL 07/80] tcg/tci: Use " Richard Henderson
2023-05-16 19:40 ` [PULL 08/80] tcg: Add 128-bit guest memory primitives Richard Henderson
2023-05-16 19:40 ` [PULL 09/80] meson: Detect atomic128 support with optimization Richard Henderson
2023-05-16 19:40 ` [PULL 10/80] tcg/i386: Add have_atomic16 Richard Henderson
2023-05-16 19:40 ` [PULL 11/80] tcg/aarch64: Detect have_lse, have_lse2 for linux Richard Henderson
2023-05-16 19:40 ` [PULL 12/80] tcg/aarch64: Detect have_lse, have_lse2 for darwin Richard Henderson
2023-05-16 19:40 ` [PULL 13/80] tcg/i386: Use full load/store helpers in user-only mode Richard Henderson
2023-05-16 19:40 ` [PULL 14/80] tcg/aarch64: " Richard Henderson
2023-05-16 19:40 ` [PULL 15/80] tcg/ppc: " Richard Henderson
2023-05-16 19:40 ` [PULL 16/80] tcg/loongarch64: " Richard Henderson
2023-05-16 19:40 ` [PULL 17/80] tcg/riscv: " Richard Henderson
2023-05-16 19:40 ` [PULL 18/80] tcg/arm: Adjust constraints on qemu_ld/st Richard Henderson
2023-05-16 19:40 ` [PULL 19/80] tcg/arm: Use full load/store helpers in user-only mode Richard Henderson
2023-05-16 19:40 ` [PULL 20/80] tcg/mips: " Richard Henderson
2023-05-16 19:40 ` [PULL 21/80] tcg/s390x: " Richard Henderson
2023-05-16 19:40 ` [PULL 22/80] tcg/sparc64: Allocate %g2 as a third temporary Richard Henderson
2023-05-16 19:40 ` [PULL 23/80] tcg/sparc64: Rename tcg_out_movi_imm13 to tcg_out_movi_s13 Richard Henderson
2023-05-16 19:40 ` [PULL 24/80] target/sparc64: Remove tcg_out_movi_s13 case from tcg_out_movi_imm32 Richard Henderson
2023-05-16 19:40 ` [PULL 25/80] tcg/sparc64: Rename tcg_out_movi_imm32 to tcg_out_movi_u32 Richard Henderson
2023-05-16 19:40 ` [PULL 26/80] tcg/sparc64: Split out tcg_out_movi_s32 Richard Henderson
2023-05-16 19:40 ` [PULL 27/80] tcg/sparc64: Use standard slow path for softmmu Richard Henderson
2023-05-16 19:40 ` [PULL 28/80] accel/tcg: Remove helper_unaligned_{ld,st} Richard Henderson
2023-05-16 19:40 ` [PULL 29/80] tcg/loongarch64: Check the host supports unaligned accesses Richard Henderson
2023-05-16 19:40 ` [PULL 30/80] tcg/loongarch64: Support softmmu " Richard Henderson
2023-05-16 19:40 ` [PULL 31/80] tcg/riscv: " Richard Henderson
2023-05-16 19:40 ` [PULL 32/80] tcg: Introduce tcg_target_has_memory_bswap Richard Henderson
2023-05-16 19:40 ` [PULL 33/80] tcg: Add INDEX_op_qemu_{ld,st}_i128 Richard Henderson
2023-05-16 19:40 ` Richard Henderson [this message]
2023-05-16 19:41 ` [PULL 35/80] tcg: Merge tcg_out_helper_load_regs into caller Richard Henderson
2023-05-16 19:41 ` [PULL 36/80] tcg: Support TCG_TYPE_I128 in tcg_out_{ld, st}_helper_{args, ret} Richard Henderson
2023-05-16 19:41 ` [PULL 37/80] tcg: Introduce atom_and_align_for_opc Richard Henderson
2023-05-16 19:41 ` [PULL 38/80] tcg/i386: Use atom_and_align_for_opc Richard Henderson
2023-05-16 19:41 ` [PULL 39/80] tcg/aarch64: " Richard Henderson
2023-05-16 19:41 ` [PULL 40/80] tcg/arm: " Richard Henderson
2023-05-16 19:41 ` [PULL 41/80] tcg/loongarch64: " Richard Henderson
2023-05-16 19:41 ` [PULL 42/80] tcg/mips: " Richard Henderson
2023-05-16 19:41 ` [PULL 43/80] tcg/ppc: " Richard Henderson
2023-05-16 19:41 ` [PULL 44/80] tcg/riscv: " Richard Henderson
2023-05-16 19:41 ` [PULL 45/80] tcg/s390x: " Richard Henderson
2023-05-16 19:41 ` [PULL 46/80] tcg/sparc64: " Richard Henderson
2023-05-16 19:41 ` [PULL 47/80] tcg/i386: Honor 64-bit atomicity in 32-bit mode Richard Henderson
2023-05-16 19:41 ` [PULL 48/80] tcg/i386: Support 128-bit load/store with have_atomic16 Richard Henderson
2023-05-16 19:41 ` [PULL 49/80] tcg/aarch64: Rename temporaries Richard Henderson
2023-05-16 19:41 ` [PULL 50/80] tcg/aarch64: Support 128-bit load/store Richard Henderson
2023-05-16 19:41 ` [PULL 51/80] tcg/ppc: " Richard Henderson
2023-05-16 19:41 ` [PULL 52/80] tcg/s390x: " Richard Henderson
2023-05-16 19:41 ` [PULL 53/80] tcg: Split out memory ops to tcg-op-ldst.c Richard Henderson
2023-05-16 19:41 ` [PULL 54/80] tcg: Widen gen_insn_data to uint64_t Richard Henderson
2023-05-16 19:41 ` [PULL 55/80] accel/tcg: Widen tcg-ldst.h addresses " Richard Henderson
2023-05-16 19:41 ` [PULL 56/80] tcg: Widen helper_{ld,st}_i128 " Richard Henderson
2023-05-16 19:41 ` [PULL 57/80] tcg: Widen helper_atomic_* " Richard Henderson
2023-05-16 19:41 ` [PULL 58/80] tcg: Widen tcg_gen_code pc_start argument " Richard Henderson
2023-05-16 19:41 ` [PULL 59/80] accel/tcg: Merge gen_mem_wrapped with plugin_gen_empty_mem_callback Richard Henderson
2023-05-16 19:41 ` [PULL 60/80] accel/tcg: Merge do_gen_mem_cb into caller Richard Henderson
2023-05-16 19:41 ` [PULL 61/80] tcg: Reduce copies for plugin_gen_mem_callbacks Richard Henderson
2023-05-16 19:41 ` [PULL 62/80] accel/tcg: Widen plugin_gen_empty_mem_callback to i64 Richard Henderson
2023-05-18 13:22 ` Peter Maydell
2023-05-16 19:41 ` [PULL 63/80] tcg: Add addr_type to TCGContext Richard Henderson
2023-05-16 19:41 ` [PULL 64/80] tcg: Remove TCGv from tcg_gen_qemu_{ld,st}_* Richard Henderson
2023-05-16 19:41 ` [PULL 65/80] tcg: Remove TCGv from tcg_gen_atomic_* Richard Henderson
2023-05-16 19:41 ` [PULL 66/80] tcg: Split INDEX_op_qemu_{ld, st}* for guest address size Richard Henderson
2023-05-16 19:41 ` [PULL 67/80] tcg/tci: Elimnate TARGET_LONG_BITS, target_ulong Richard Henderson
2023-05-16 19:41 ` [PULL 68/80] tcg/i386: Always enable TCG_TARGET_HAS_extr[lh]_i64_i32 Richard Henderson
2023-05-16 19:41 ` [PULL 69/80] tcg/i386: Conditionalize tcg_out_extu_i32_i64 Richard Henderson
2023-05-16 19:41 ` [PULL 70/80] tcg/i386: Adjust type of tlb_mask Richard Henderson
2023-05-16 19:41 ` [PULL 71/80] tcg/i386: Remove TARGET_LONG_BITS, TCG_TYPE_TL Richard Henderson
2023-05-16 19:41 ` [PULL 72/80] tcg/arm: Remove TARGET_LONG_BITS Richard Henderson
2023-05-16 19:41 ` [PULL 73/80] tcg/aarch64: Remove USE_GUEST_BASE Richard Henderson
2023-05-16 19:41 ` [PULL 74/80] tcg/aarch64: Remove TARGET_LONG_BITS, TCG_TYPE_TL Richard Henderson
2023-05-16 19:41 ` [PULL 75/80] tcg/loongarch64: " Richard Henderson
2023-05-16 19:41 ` [PULL 76/80] tcg/mips: " Richard Henderson
2023-05-16 19:41 ` [PULL 77/80] tcg: " Richard Henderson
2023-05-16 19:41 ` [PULL 78/80] tcg: Add page_bits and page_mask to TCGContext Richard Henderson
2023-05-16 19:41 ` [PULL 79/80] tcg: Add tlb_dyn_max_bits " Richard Henderson
2023-05-16 19:41 ` [PULL 80/80] tcg: Split out exec/user/guest-base.h Richard Henderson
2023-05-17 15:11 ` [PULL 00/80] tcg patch queue Peter Maydell
2023-05-17 19:16 ` Richard Henderson
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