[PATCH RFC 0/5] hw/cxl: Type 2 Device RFC

[Ira Weiny <ira.weiny@intel.com>]

Type 2 devices are not yet a reality.  Developing core kernel support
is difficult without some test device to model against.

Define a type 2 device 'cxl-accel'.  This device is derived from the
type 3 device and retains all that functionality for now.

Mock up a couple of accelerator features (Back Invalidate [BI] and
Unordered IO [UIO]) as examples for the RFC.  These have no
functionality other than to report the features as present for software
to key off of.

Defining these devices in qemu can be done with the following example:

...
  -device cxl-accel,bus=sw0p0,volatile-memdev=cxl-ac-mem5,id=cxl-dev5,sn=0xCAFE0005
...

NOTE: I'm leaving off Michael Tsirkin for now because this is really
rough and I'm mainly sending it out because it was talked about in the
CXL community call on 5/16.

Not-Yet-Signed-off-by: Ira Weiny <ira.weiny@intel.com>
---
Ira Weiny (5):
      hw/cxl: Use define for build bug detection
      hw/cxl: Refactor component register initialization
      hw/cxl: Derive a CXL accelerator device from Type-3
      hw/cxl/accel: Add Back-Invalidate decoder capbility structure
      hw/cxl: Add UIO HDM decoder register fields

 docs/system/devices/cxl.rst    | 11 ++++++
 hw/cxl/cxl-component-utils.c   | 80 +++++++++++++++++++-----------------------
 hw/mem/cxl_type3.c             | 39 ++++++++++++++++++++
 include/hw/cxl/cxl_component.h | 51 +++++++++++++++++++--------
 include/hw/cxl/cxl_device.h    | 16 +++++++++
 include/hw/pci/pci_ids.h       |  1 +
 6 files changed, 141 insertions(+), 57 deletions(-)
---
base-commit: 8eb2a03258313f404ca0c8609a8f9009b9b4318c
change-id: 20230517-rfc-type2-dev-c2d661a29d96

Best regards,
-- 
Ira Weiny <ira.weiny@intel.com>