From: Weiwei Li <liweiwei@iscas.ac.cn>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org,
wangjunqiang@iscas.ac.cn, lazyparser@gmail.com,
Weiwei Li <liweiwei@iscas.ac.cn>
Subject: [PATCH v6 10/12] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes
Date: Wed, 17 May 2023 17:15:17 +0800 [thread overview]
Message-ID: <20230517091519.34439-11-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20230517091519.34439-1-liweiwei@iscas.ac.cn>
TLB needn't be flushed when pmpcfg/pmpaddr don't changes.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/pmp.c | 28 ++++++++++++++++++----------
1 file changed, 18 insertions(+), 10 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 70fb2327f7..37b25e9b34 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -26,7 +26,7 @@
#include "trace.h"
#include "exec/exec-all.h"
-static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
+static bool pmp_write_cfg(CPURISCVState *env, uint32_t addr_index,
uint8_t val);
static uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t addr_index);
static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index);
@@ -83,7 +83,7 @@ static inline uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t pmp_index)
* Accessor to set the cfg reg for a specific PMP/HART
* Bounds checks and relevant lock bit.
*/
-static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
+static bool pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
{
if (pmp_index < MAX_RISCV_PMPS) {
bool locked = true;
@@ -119,14 +119,17 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
if (locked) {
qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpcfg write - locked\n");
- } else {
+ } else if (env->pmp_state.pmp[pmp_index].cfg_reg != val) {
env->pmp_state.pmp[pmp_index].cfg_reg = val;
pmp_update_rule(env, pmp_index);
+ return true;
}
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"ignoring pmpcfg write - out of bounds\n");
}
+
+ return false;
}
static void pmp_decode_napot(target_ulong a, target_ulong *sa,
@@ -467,16 +470,19 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
int i;
uint8_t cfg_val;
int pmpcfg_nums = 2 << riscv_cpu_mxl(env);
+ bool modified = false;
trace_pmpcfg_csr_write(env->mhartid, reg_index, val);
for (i = 0; i < pmpcfg_nums; i++) {
cfg_val = (val >> 8 * i) & 0xff;
- pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
+ modified |= pmp_write_cfg(env, (reg_index * 4) + i, cfg_val);
}
/* If PMP permission of any addr has been changed, flush TLB pages. */
- tlb_flush(env_cpu(env));
+ if (modified) {
+ tlb_flush(env_cpu(env));
+ }
}
@@ -526,12 +532,14 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
}
if (!pmp_is_locked(env, addr_index)) {
- env->pmp_state.pmp[addr_index].addr_reg = val;
- pmp_update_rule_addr(env, addr_index);
- if (is_next_cfg_tor) {
- pmp_update_rule_addr(env, addr_index + 1);
+ if (env->pmp_state.pmp[addr_index].addr_reg != val) {
+ env->pmp_state.pmp[addr_index].addr_reg = val;
+ pmp_update_rule_addr(env, addr_index);
+ if (is_next_cfg_tor) {
+ pmp_update_rule_addr(env, addr_index + 1);
+ }
+ tlb_flush(env_cpu(env));
}
- tlb_flush(env_cpu(env));
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"ignoring pmpaddr write - locked\n");
--
2.25.1
next prev parent reply other threads:[~2023-05-17 9:17 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-17 9:15 [PATCH v6 00/12] target/riscv: Fix PMP related problem Weiwei Li
2023-05-17 9:15 ` [PATCH v6 01/12] target/riscv: Update pmp_get_tlb_size() Weiwei Li
2023-05-17 9:15 ` [PATCH v6 02/12] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp Weiwei Li
2023-05-17 9:15 ` [PATCH v6 03/12] target/riscv: Make the short cut really work in pmp_hart_has_privs Weiwei Li
2023-05-17 9:15 ` [PATCH v6 04/12] target/riscv: Change the return type of pmp_hart_has_privs() to bool Weiwei Li
2023-05-17 9:15 ` [PATCH v6 05/12] target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled Weiwei Li
2023-05-17 9:15 ` [PATCH v6 06/12] target/riscv: Remove unused paramters in pmp_hart_has_privs_default() Weiwei Li
2023-05-17 9:15 ` [PATCH v6 07/12] target/riscv: Flush TLB when MMWP or MML bits are changed Weiwei Li
2023-05-17 9:15 ` [PATCH v6 08/12] target/riscv: Update the next rule addr in pmpaddr_csr_write() Weiwei Li
2023-05-17 9:15 ` [PATCH v6 09/12] target/riscv: Flush TLB when pmpaddr is updated Weiwei Li
2023-05-17 9:15 ` Weiwei Li [this message]
2023-05-17 9:15 ` [PATCH v6 11/12] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write Weiwei Li
2023-05-17 9:15 ` [PATCH v6 12/12] target/riscv: Deny access if access is partially inside the PMP entry Weiwei Li
2023-05-18 9:46 ` [PATCH v6 00/12] target/riscv: Fix PMP related problem Alistair Francis
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