From: Weiwei Li <liweiwei@iscas.ac.cn>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org,
wangjunqiang@iscas.ac.cn, lazyparser@gmail.com,
Weiwei Li <liweiwei@iscas.ac.cn>
Subject: [PATCH v6 03/12] target/riscv: Make the short cut really work in pmp_hart_has_privs
Date: Wed, 17 May 2023 17:15:10 +0800 [thread overview]
Message-ID: <20230517091519.34439-4-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20230517091519.34439-1-liweiwei@iscas.ac.cn>
Return the result directly for short cut, since We needn't do the
following check on the PMP entries if there is no PMP rules.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/pmp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 406cff74f2..9cc5c0e9e8 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -316,6 +316,7 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
allowed_privs, mode)) {
ret = MAX_RISCV_PMPS;
}
+ return ret;
}
if (size == 0) {
--
2.25.1
next prev parent reply other threads:[~2023-05-17 9:17 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-17 9:15 [PATCH v6 00/12] target/riscv: Fix PMP related problem Weiwei Li
2023-05-17 9:15 ` [PATCH v6 01/12] target/riscv: Update pmp_get_tlb_size() Weiwei Li
2023-05-17 9:15 ` [PATCH v6 02/12] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp Weiwei Li
2023-05-17 9:15 ` Weiwei Li [this message]
2023-05-17 9:15 ` [PATCH v6 04/12] target/riscv: Change the return type of pmp_hart_has_privs() to bool Weiwei Li
2023-05-17 9:15 ` [PATCH v6 05/12] target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled Weiwei Li
2023-05-17 9:15 ` [PATCH v6 06/12] target/riscv: Remove unused paramters in pmp_hart_has_privs_default() Weiwei Li
2023-05-17 9:15 ` [PATCH v6 07/12] target/riscv: Flush TLB when MMWP or MML bits are changed Weiwei Li
2023-05-17 9:15 ` [PATCH v6 08/12] target/riscv: Update the next rule addr in pmpaddr_csr_write() Weiwei Li
2023-05-17 9:15 ` [PATCH v6 09/12] target/riscv: Flush TLB when pmpaddr is updated Weiwei Li
2023-05-17 9:15 ` [PATCH v6 10/12] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes Weiwei Li
2023-05-17 9:15 ` [PATCH v6 11/12] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write Weiwei Li
2023-05-17 9:15 ` [PATCH v6 12/12] target/riscv: Deny access if access is partially inside the PMP entry Weiwei Li
2023-05-18 9:46 ` [PATCH v6 00/12] target/riscv: Fix PMP related problem Alistair Francis
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