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From: Weiwei Li <liweiwei@iscas.ac.cn>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
	bin.meng@windriver.com, dbarboza@ventanamicro.com,
	zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org,
	wangjunqiang@iscas.ac.cn, lazyparser@gmail.com,
	Weiwei Li <liweiwei@iscas.ac.cn>
Subject: [PATCH v6 04/12] target/riscv: Change the return type of pmp_hart_has_privs() to bool
Date: Wed, 17 May 2023 17:15:11 +0800	[thread overview]
Message-ID: <20230517091519.34439-5-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20230517091519.34439-1-liweiwei@iscas.ac.cn>

We no longer need the pmp_index for matched PMP entry now.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu_helper.c |  8 ++++----
 target/riscv/pmp.c        | 32 +++++++++++++-------------------
 target/riscv/pmp.h        |  8 ++++----
 3 files changed, 21 insertions(+), 27 deletions(-)

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 15eafb342d..7c736c256e 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -696,16 +696,16 @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot, hwaddr addr,
                                     int mode)
 {
     pmp_priv_t pmp_priv;
-    int pmp_index = -1;
+    bool pmp_has_privs;
 
     if (!riscv_cpu_cfg(env)->pmp) {
         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
         return TRANSLATE_SUCCESS;
     }
 
-    pmp_index = pmp_hart_has_privs(env, addr, size, 1 << access_type,
-                                   &pmp_priv, mode);
-    if (pmp_index < 0) {
+    pmp_has_privs = pmp_hart_has_privs(env, addr, size, 1 << access_type,
+                                       &pmp_priv, mode);
+    if (!pmp_has_privs) {
         *prot = 0;
         return TRANSLATE_PMP_FAIL;
     }
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 9cc5c0e9e8..1d42cfb5f8 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -296,27 +296,23 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
 
 /*
  * Check if the address has required RWX privs to complete desired operation
- * Return PMP rule index if a pmp rule match
- * Return MAX_RISCV_PMPS if default match
- * Return negtive value if no match
+ * Return true if a pmp rule match or default match
+ * Return false if no match
  */
-int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
-                       target_ulong size, pmp_priv_t privs,
-                       pmp_priv_t *allowed_privs, target_ulong mode)
+bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
+                        target_ulong size, pmp_priv_t privs,
+                        pmp_priv_t *allowed_privs, target_ulong mode)
 {
     int i = 0;
-    int ret = -1;
+    bool ret = false;
     int pmp_size = 0;
     target_ulong s = 0;
     target_ulong e = 0;
 
     /* Short cut if no rules */
     if (0 == pmp_get_num_rules(env)) {
-        if (pmp_hart_has_privs_default(env, addr, size, privs,
-                                       allowed_privs, mode)) {
-            ret = MAX_RISCV_PMPS;
-        }
-        return ret;
+        return pmp_hart_has_privs_default(env, addr, size, privs,
+                                          allowed_privs, mode);
     }
 
     if (size == 0) {
@@ -345,7 +341,7 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
         if ((s + e) == 1) {
             qemu_log_mask(LOG_GUEST_ERROR,
                           "pmp violation - access is partially inside\n");
-            ret = -1;
+            ret = false;
             break;
         }
 
@@ -453,17 +449,15 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
              * defined with PMP must be used. We shouldn't fallback on
              * finding default privileges.
              */
-            ret = i;
+            ret = true;
             break;
         }
     }
 
     /* No rule matched */
-    if (ret == -1) {
-        if (pmp_hart_has_privs_default(env, addr, size, privs,
-                                       allowed_privs, mode)) {
-            ret = MAX_RISCV_PMPS;
-        }
+    if (!ret) {
+        ret = pmp_hart_has_privs_default(env, addr, size, privs,
+                                         allowed_privs, mode);
     }
 
     return ret;
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index 0a7e24750b..cf5c99f8e6 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -72,10 +72,10 @@ target_ulong mseccfg_csr_read(CPURISCVState *env);
 void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
                        target_ulong val);
 target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
-int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
-                       target_ulong size, pmp_priv_t privs,
-                       pmp_priv_t *allowed_privs,
-                       target_ulong mode);
+bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
+                        target_ulong size, pmp_priv_t privs,
+                        pmp_priv_t *allowed_privs,
+                        target_ulong mode);
 target_ulong pmp_get_tlb_size(CPURISCVState *env, target_ulong addr);
 void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index);
 void pmp_update_rule_nums(CPURISCVState *env);
-- 
2.25.1



  parent reply	other threads:[~2023-05-17  9:16 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-17  9:15 [PATCH v6 00/12] target/riscv: Fix PMP related problem Weiwei Li
2023-05-17  9:15 ` [PATCH v6 01/12] target/riscv: Update pmp_get_tlb_size() Weiwei Li
2023-05-17  9:15 ` [PATCH v6 02/12] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp Weiwei Li
2023-05-17  9:15 ` [PATCH v6 03/12] target/riscv: Make the short cut really work in pmp_hart_has_privs Weiwei Li
2023-05-17  9:15 ` Weiwei Li [this message]
2023-05-17  9:15 ` [PATCH v6 05/12] target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled Weiwei Li
2023-05-17  9:15 ` [PATCH v6 06/12] target/riscv: Remove unused paramters in pmp_hart_has_privs_default() Weiwei Li
2023-05-17  9:15 ` [PATCH v6 07/12] target/riscv: Flush TLB when MMWP or MML bits are changed Weiwei Li
2023-05-17  9:15 ` [PATCH v6 08/12] target/riscv: Update the next rule addr in pmpaddr_csr_write() Weiwei Li
2023-05-17  9:15 ` [PATCH v6 09/12] target/riscv: Flush TLB when pmpaddr is updated Weiwei Li
2023-05-17  9:15 ` [PATCH v6 10/12] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes Weiwei Li
2023-05-17  9:15 ` [PATCH v6 11/12] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write Weiwei Li
2023-05-17  9:15 ` [PATCH v6 12/12] target/riscv: Deny access if access is partially inside the PMP entry Weiwei Li
2023-05-18  9:46 ` [PATCH v6 00/12] target/riscv: Fix PMP related problem Alistair Francis

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