* [PATCH v1 0/2] Add LoongArch cpu arch_id support
@ 2023-05-18 1:41 Song Gao
2023-05-18 1:41 ` [PATCH v1 1/2] hw/loongarch/virt: Add " Song Gao
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Song Gao @ 2023-05-18 1:41 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, peter.maydell, philmd, imammedo, anisinha, mst,
alex.bennee, maobibo, yangxiaojuan
1 Add LoongArch cpu arch_id support;
2 Fill Acpi table with arch_id;
3 set physical cpuid route for LoongArch ipi device.
Song Gao (2):
hw/loongarch/virt: Add cpu arch_id support
hw/intc: Set physical cpuid route for LoongArch ipi device
hw/intc/loongarch_ipi.c | 44 ++++++++++++++++++++++++++++++++-------
hw/loongarch/acpi-build.c | 20 ++++++++++++------
hw/loongarch/virt.c | 35 +++++++++++++++++++++++++++++--
target/loongarch/cpu.h | 2 ++
4 files changed, 86 insertions(+), 15 deletions(-)
--
2.39.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v1 1/2] hw/loongarch/virt: Add cpu arch_id support 2023-05-18 1:41 [PATCH v1 0/2] Add LoongArch cpu arch_id support Song Gao @ 2023-05-18 1:41 ` Song Gao 2023-05-30 11:53 ` Tianrui Zhao 2023-05-18 1:41 ` [PATCH v1 2/2] hw/intc: Set physical cpuid route for LoongArch ipi device Song Gao 2023-05-30 8:40 ` [PATCH v1 0/2] Add LoongArch cpu arch_id support Song Gao 2 siblings, 1 reply; 6+ messages in thread From: Song Gao @ 2023-05-18 1:41 UTC (permalink / raw) To: qemu-devel Cc: richard.henderson, peter.maydell, philmd, imammedo, anisinha, mst, alex.bennee, maobibo, yangxiaojuan With acpi madt table, there is cpu physical coreid, which may be different with logical id in qemu. This patch adds cpu arch_id support, and fill madt table with arch_id. For the present cpu arch_id is still equal to logical id. Signed-off-by: Song Gao <gaosong@loongson.cn> --- hw/loongarch/acpi-build.c | 20 ++++++++++++++------ hw/loongarch/virt.c | 34 ++++++++++++++++++++++++++++++++-- 2 files changed, 46 insertions(+), 8 deletions(-) diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c index 8e3ce07367..232344e1c7 100644 --- a/hw/loongarch/acpi-build.c +++ b/hw/loongarch/acpi-build.c @@ -107,7 +107,9 @@ static void build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams) { MachineState *ms = MACHINE(lams); - int i; + MachineClass *mc = MACHINE_GET_CLASS(ms); + const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); + int i, arch_id; AcpiTable table = { .sig = "APIC", .rev = 1, .oem_id = lams->oem_id, .oem_table_id = lams->oem_table_id }; @@ -117,13 +119,15 @@ build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams) build_append_int_noprefix(table_data, 0, 4); build_append_int_noprefix(table_data, 1 /* PCAT_COMPAT */, 4); /* Flags */ - for (i = 0; i < ms->smp.cpus; i++) { + for (i = 0; i < arch_ids->len; i++) { /* Processor Core Interrupt Controller Structure */ + arch_id = arch_ids->cpus[i].arch_id; + build_append_int_noprefix(table_data, 17, 1); /* Type */ build_append_int_noprefix(table_data, 15, 1); /* Length */ build_append_int_noprefix(table_data, 1, 1); /* Version */ build_append_int_noprefix(table_data, i + 1, 4); /* ACPI Processor ID */ - build_append_int_noprefix(table_data, i, 4); /* Core ID */ + build_append_int_noprefix(table_data, arch_id, 4); /* Core ID */ build_append_int_noprefix(table_data, 1, 4); /* Flags */ } @@ -159,9 +163,11 @@ build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams) static void build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) { - uint64_t i; + int i, arch_id; LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); MachineState *ms = MACHINE(lams); + MachineClass *mc = MACHINE_GET_CLASS(ms); + const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = lams->oem_id, .oem_table_id = lams->oem_table_id }; @@ -169,13 +175,15 @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) build_append_int_noprefix(table_data, 1, 4); /* Reserved */ build_append_int_noprefix(table_data, 0, 8); /* Reserved */ - for (i = 0; i < ms->smp.cpus; ++i) { + for (i = 0; i < arch_ids->len; ++i) { + arch_id = arch_ids->cpus[i].arch_id; + /* Processor Local APIC/SAPIC Affinity Structure */ build_append_int_noprefix(table_data, 0, 1); /* Type */ build_append_int_noprefix(table_data, 16, 1); /* Length */ /* Proximity Domain [7:0] */ build_append_int_noprefix(table_data, 0, 1); - build_append_int_noprefix(table_data, i, 1); /* APIC ID */ + build_append_int_noprefix(table_data, arch_id, 1); /* APIC ID */ /* Flags, Table 5-36 */ build_append_int_noprefix(table_data, 1, 4); build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */ diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 2b7588e32a..83c1e43ff5 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -770,6 +770,9 @@ static void loongarch_init(MachineState *machine) LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); int i; hwaddr fdt_base; + const CPUArchIdList *possible_cpus; + MachineClass *mc = MACHINE_GET_CLASS(machine); + CPUState *cpu; if (!cpu_model) { cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); @@ -786,8 +789,12 @@ static void loongarch_init(MachineState *machine) } create_fdt(lams); /* Init CPUs */ - for (i = 0; i < machine->smp.cpus; i++) { - cpu_create(machine->cpu_type); + + possible_cpus = mc->possible_cpu_arch_ids(machine); + for (i = 0; i < possible_cpus->len; i++) { + cpu = cpu_create(machine->cpu_type); + cpu->cpu_index = i; + machine->possible_cpus->cpus[i].cpu = OBJECT(cpu); } fdt_add_cpu_nodes(lams); /* Add memory region */ @@ -1021,6 +1028,28 @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, return NULL; } +static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) +{ + int n; + unsigned int max_cpus = ms->smp.max_cpus; + + if (ms->possible_cpus) { + assert(ms->possible_cpus->len == max_cpus); + return ms->possible_cpus; + } + + ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + + sizeof(CPUArchId) * max_cpus); + ms->possible_cpus->len = max_cpus; + for (n = 0; n < ms->possible_cpus->len; n++) { + ms->possible_cpus->cpus[n].type = ms->cpu_type; + ms->possible_cpus->cpus[n].arch_id = n; + ms->possible_cpus->cpus[n].props.has_core_id = true; + ms->possible_cpus->cpus[n].props.core_id = n; + } + return ms->possible_cpus; +} + static void loongarch_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -1037,6 +1066,7 @@ static void loongarch_class_init(ObjectClass *oc, void *data) mc->block_default_type = IF_VIRTIO; mc->default_boot_order = "c"; mc->no_cdrom = 1; + mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; mc->get_hotplug_handler = virt_machine_get_hotplug_handler; hc->plug = loongarch_machine_device_plug_cb; hc->pre_plug = virt_machine_device_pre_plug; -- 2.39.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v1 1/2] hw/loongarch/virt: Add cpu arch_id support 2023-05-18 1:41 ` [PATCH v1 1/2] hw/loongarch/virt: Add " Song Gao @ 2023-05-30 11:53 ` Tianrui Zhao 2023-05-30 12:23 ` Song Gao 0 siblings, 1 reply; 6+ messages in thread From: Tianrui Zhao @ 2023-05-30 11:53 UTC (permalink / raw) To: Song Gao, qemu-devel Cc: richard.henderson, peter.maydell, philmd, imammedo, anisinha, mst, alex.bennee, maobibo, yangxiaojuan 在 2023年05月18日 09:41, Song Gao 写道: > With acpi madt table, there is cpu physical coreid, which may > be different with logical id in qemu. This patch adds cpu arch_id > support, and fill madt table with arch_id. For the present cpu > arch_id is still equal to logical id. > > Signed-off-by: Song Gao <gaosong@loongson.cn> > --- > hw/loongarch/acpi-build.c | 20 ++++++++++++++------ > hw/loongarch/virt.c | 34 ++++++++++++++++++++++++++++++++-- > 2 files changed, 46 insertions(+), 8 deletions(-) > > diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c > index 8e3ce07367..232344e1c7 100644 > --- a/hw/loongarch/acpi-build.c > +++ b/hw/loongarch/acpi-build.c > @@ -107,7 +107,9 @@ static void > build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams) > { > MachineState *ms = MACHINE(lams); > - int i; > + MachineClass *mc = MACHINE_GET_CLASS(ms); > + const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); > + int i, arch_id; > AcpiTable table = { .sig = "APIC", .rev = 1, .oem_id = lams->oem_id, > .oem_table_id = lams->oem_table_id }; > > @@ -117,13 +119,15 @@ build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams) > build_append_int_noprefix(table_data, 0, 4); > build_append_int_noprefix(table_data, 1 /* PCAT_COMPAT */, 4); /* Flags */ > > - for (i = 0; i < ms->smp.cpus; i++) { > + for (i = 0; i < arch_ids->len; i++) { > /* Processor Core Interrupt Controller Structure */ > + arch_id = arch_ids->cpus[i].arch_id; > + > build_append_int_noprefix(table_data, 17, 1); /* Type */ > build_append_int_noprefix(table_data, 15, 1); /* Length */ > build_append_int_noprefix(table_data, 1, 1); /* Version */ > build_append_int_noprefix(table_data, i + 1, 4); /* ACPI Processor ID */ > - build_append_int_noprefix(table_data, i, 4); /* Core ID */ > + build_append_int_noprefix(table_data, arch_id, 4); /* Core ID */ > build_append_int_noprefix(table_data, 1, 4); /* Flags */ > } > > @@ -159,9 +163,11 @@ build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams) > static void > build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) > { > - uint64_t i; > + int i, arch_id; > LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); > MachineState *ms = MACHINE(lams); > + MachineClass *mc = MACHINE_GET_CLASS(ms); > + const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); > AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = lams->oem_id, > .oem_table_id = lams->oem_table_id }; > > @@ -169,13 +175,15 @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) > build_append_int_noprefix(table_data, 1, 4); /* Reserved */ > build_append_int_noprefix(table_data, 0, 8); /* Reserved */ > > - for (i = 0; i < ms->smp.cpus; ++i) { > + for (i = 0; i < arch_ids->len; ++i) { > + arch_id = arch_ids->cpus[i].arch_id; > + > /* Processor Local APIC/SAPIC Affinity Structure */ > build_append_int_noprefix(table_data, 0, 1); /* Type */ > build_append_int_noprefix(table_data, 16, 1); /* Length */ > /* Proximity Domain [7:0] */ > build_append_int_noprefix(table_data, 0, 1); > - build_append_int_noprefix(table_data, i, 1); /* APIC ID */ > + build_append_int_noprefix(table_data, arch_id, 1); /* APIC ID */ > /* Flags, Table 5-36 */ > build_append_int_noprefix(table_data, 1, 4); > build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */ > diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c > index 2b7588e32a..83c1e43ff5 100644 > --- a/hw/loongarch/virt.c > +++ b/hw/loongarch/virt.c > @@ -770,6 +770,9 @@ static void loongarch_init(MachineState *machine) > LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); > int i; > hwaddr fdt_base; > + const CPUArchIdList *possible_cpus; > + MachineClass *mc = MACHINE_GET_CLASS(machine); > + CPUState *cpu; > > if (!cpu_model) { > cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); > @@ -786,8 +789,12 @@ static void loongarch_init(MachineState *machine) > } > create_fdt(lams); > /* Init CPUs */ > - for (i = 0; i < machine->smp.cpus; i++) { > - cpu_create(machine->cpu_type); > + > + possible_cpus = mc->possible_cpu_arch_ids(machine); > + for (i = 0; i < possible_cpus->len; i++) { > + cpu = cpu_create(machine->cpu_type); > + cpu->cpu_index = i; > + machine->possible_cpus->cpus[i].cpu = OBJECT(cpu); > } > fdt_add_cpu_nodes(lams); > /* Add memory region */ > @@ -1021,6 +1028,28 @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, > return NULL; > } > > +static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) > +{ > + int n; > + unsigned int max_cpus = ms->smp.max_cpus; > + > + if (ms->possible_cpus) { > + assert(ms->possible_cpus->len == max_cpus); > + return ms->possible_cpus; > + } > + > + ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + > + sizeof(CPUArchId) * max_cpus); > + ms->possible_cpus->len = max_cpus; > + for (n = 0; n < ms->possible_cpus->len; n++) { > + ms->possible_cpus->cpus[n].type = ms->cpu_type; > + ms->possible_cpus->cpus[n].arch_id = n; > + ms->possible_cpus->cpus[n].props.has_core_id = true; > + ms->possible_cpus->cpus[n].props.core_id = n; Should this be core_id = (n / ms->smp.threads) % ms->smp.cores ? Thanks Tianrui Zhao > + } > + return ms->possible_cpus; > +} > + > static void loongarch_class_init(ObjectClass *oc, void *data) > { > MachineClass *mc = MACHINE_CLASS(oc); > @@ -1037,6 +1066,7 @@ static void loongarch_class_init(ObjectClass *oc, void *data) > mc->block_default_type = IF_VIRTIO; > mc->default_boot_order = "c"; > mc->no_cdrom = 1; > + mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; > mc->get_hotplug_handler = virt_machine_get_hotplug_handler; > hc->plug = loongarch_machine_device_plug_cb; > hc->pre_plug = virt_machine_device_pre_plug; ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v1 1/2] hw/loongarch/virt: Add cpu arch_id support 2023-05-30 11:53 ` Tianrui Zhao @ 2023-05-30 12:23 ` Song Gao 0 siblings, 0 replies; 6+ messages in thread From: Song Gao @ 2023-05-30 12:23 UTC (permalink / raw) To: Tianrui Zhao, qemu-devel Cc: richard.henderson, peter.maydell, philmd, imammedo, anisinha, mst, alex.bennee, maobibo, yangxiaojuan 在 2023/5/30 下午7:53, Tianrui Zhao 写道: > > > 在 2023年05月18日 09:41, Song Gao 写道: >> With acpi madt table, there is cpu physical coreid, which may >> be different with logical id in qemu. This patch adds cpu arch_id >> support, and fill madt table with arch_id. For the present cpu >> arch_id is still equal to logical id. >> >> Signed-off-by: Song Gao <gaosong@loongson.cn> >> --- >> hw/loongarch/acpi-build.c | 20 ++++++++++++++------ >> hw/loongarch/virt.c | 34 ++++++++++++++++++++++++++++++++-- >> 2 files changed, 46 insertions(+), 8 deletions(-) >> >> diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c >> index 8e3ce07367..232344e1c7 100644 >> --- a/hw/loongarch/acpi-build.c >> +++ b/hw/loongarch/acpi-build.c >> @@ -107,7 +107,9 @@ static void >> build_madt(GArray *table_data, BIOSLinker *linker, >> LoongArchMachineState *lams) >> { >> MachineState *ms = MACHINE(lams); >> - int i; >> + MachineClass *mc = MACHINE_GET_CLASS(ms); >> + const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); >> + int i, arch_id; >> AcpiTable table = { .sig = "APIC", .rev = 1, .oem_id = >> lams->oem_id, >> .oem_table_id = lams->oem_table_id }; >> @@ -117,13 +119,15 @@ build_madt(GArray *table_data, BIOSLinker >> *linker, LoongArchMachineState *lams) >> build_append_int_noprefix(table_data, 0, 4); >> build_append_int_noprefix(table_data, 1 /* PCAT_COMPAT */, 4); >> /* Flags */ >> - for (i = 0; i < ms->smp.cpus; i++) { >> + for (i = 0; i < arch_ids->len; i++) { >> /* Processor Core Interrupt Controller Structure */ >> + arch_id = arch_ids->cpus[i].arch_id; >> + >> build_append_int_noprefix(table_data, 17, 1); /* Type */ >> build_append_int_noprefix(table_data, 15, 1); /* Length */ >> build_append_int_noprefix(table_data, 1, 1); /* Version */ >> build_append_int_noprefix(table_data, i + 1, 4); /* ACPI >> Processor ID */ >> - build_append_int_noprefix(table_data, i, 4); /* Core ID */ >> + build_append_int_noprefix(table_data, arch_id, 4); /* Core >> ID */ >> build_append_int_noprefix(table_data, 1, 4); /* Flags */ >> } >> @@ -159,9 +163,11 @@ build_madt(GArray *table_data, BIOSLinker >> *linker, LoongArchMachineState *lams) >> static void >> build_srat(GArray *table_data, BIOSLinker *linker, MachineState >> *machine) >> { >> - uint64_t i; >> + int i, arch_id; >> LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); >> MachineState *ms = MACHINE(lams); >> + MachineClass *mc = MACHINE_GET_CLASS(ms); >> + const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms); >> AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = >> lams->oem_id, >> .oem_table_id = lams->oem_table_id }; >> @@ -169,13 +175,15 @@ build_srat(GArray *table_data, BIOSLinker >> *linker, MachineState *machine) >> build_append_int_noprefix(table_data, 1, 4); /* Reserved */ >> build_append_int_noprefix(table_data, 0, 8); /* Reserved */ >> - for (i = 0; i < ms->smp.cpus; ++i) { >> + for (i = 0; i < arch_ids->len; ++i) { >> + arch_id = arch_ids->cpus[i].arch_id; >> + >> /* Processor Local APIC/SAPIC Affinity Structure */ >> build_append_int_noprefix(table_data, 0, 1); /* Type */ >> build_append_int_noprefix(table_data, 16, 1); /* Length */ >> /* Proximity Domain [7:0] */ >> build_append_int_noprefix(table_data, 0, 1); >> - build_append_int_noprefix(table_data, i, 1); /* APIC ID */ >> + build_append_int_noprefix(table_data, arch_id, 1); /* APIC >> ID */ >> /* Flags, Table 5-36 */ >> build_append_int_noprefix(table_data, 1, 4); >> build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC >> EID */ >> diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c >> index 2b7588e32a..83c1e43ff5 100644 >> --- a/hw/loongarch/virt.c >> +++ b/hw/loongarch/virt.c >> @@ -770,6 +770,9 @@ static void loongarch_init(MachineState *machine) >> LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); >> int i; >> hwaddr fdt_base; >> + const CPUArchIdList *possible_cpus; >> + MachineClass *mc = MACHINE_GET_CLASS(machine); >> + CPUState *cpu; >> if (!cpu_model) { >> cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); >> @@ -786,8 +789,12 @@ static void loongarch_init(MachineState *machine) >> } >> create_fdt(lams); >> /* Init CPUs */ >> - for (i = 0; i < machine->smp.cpus; i++) { >> - cpu_create(machine->cpu_type); >> + >> + possible_cpus = mc->possible_cpu_arch_ids(machine); >> + for (i = 0; i < possible_cpus->len; i++) { >> + cpu = cpu_create(machine->cpu_type); >> + cpu->cpu_index = i; >> + machine->possible_cpus->cpus[i].cpu = OBJECT(cpu); >> } >> fdt_add_cpu_nodes(lams); >> /* Add memory region */ >> @@ -1021,6 +1028,28 @@ static HotplugHandler >> *virt_machine_get_hotplug_handler(MachineState *machine, >> return NULL; >> } >> +static const CPUArchIdList >> *virt_possible_cpu_arch_ids(MachineState *ms) >> +{ >> + int n; >> + unsigned int max_cpus = ms->smp.max_cpus; >> + >> + if (ms->possible_cpus) { >> + assert(ms->possible_cpus->len == max_cpus); >> + return ms->possible_cpus; >> + } >> + >> + ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + >> + sizeof(CPUArchId) * max_cpus); >> + ms->possible_cpus->len = max_cpus; >> + for (n = 0; n < ms->possible_cpus->len; n++) { >> + ms->possible_cpus->cpus[n].type = ms->cpu_type; >> + ms->possible_cpus->cpus[n].arch_id = n; >> + ms->possible_cpus->cpus[n].props.has_core_id = true; >> + ms->possible_cpus->cpus[n].props.core_id = n; > Should this be core_id = (n / ms->smp.threads) % ms->smp.cores ? > The LoongArch kernel is' t support set smp.threads. Thanks. Song Gao >> + } >> + return ms->possible_cpus; >> +} >> + >> static void loongarch_class_init(ObjectClass *oc, void *data) >> { >> MachineClass *mc = MACHINE_CLASS(oc); >> @@ -1037,6 +1066,7 @@ static void loongarch_class_init(ObjectClass >> *oc, void *data) >> mc->block_default_type = IF_VIRTIO; >> mc->default_boot_order = "c"; >> mc->no_cdrom = 1; >> + mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; >> mc->get_hotplug_handler = virt_machine_get_hotplug_handler; >> hc->plug = loongarch_machine_device_plug_cb; >> hc->pre_plug = virt_machine_device_pre_plug; ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v1 2/2] hw/intc: Set physical cpuid route for LoongArch ipi device 2023-05-18 1:41 [PATCH v1 0/2] Add LoongArch cpu arch_id support Song Gao 2023-05-18 1:41 ` [PATCH v1 1/2] hw/loongarch/virt: Add " Song Gao @ 2023-05-18 1:41 ` Song Gao 2023-05-30 8:40 ` [PATCH v1 0/2] Add LoongArch cpu arch_id support Song Gao 2 siblings, 0 replies; 6+ messages in thread From: Song Gao @ 2023-05-18 1:41 UTC (permalink / raw) To: qemu-devel Cc: richard.henderson, peter.maydell, philmd, imammedo, anisinha, mst, alex.bennee, maobibo, yangxiaojuan LoongArch ipi device uses physical cpuid to route to different vcpus rather logical cpuid, and the physical cpuid is the same with cpuid in acpi dsdt and srat table. Signed-off-by: Song Gao <gaosong@loongson.cn> --- hw/intc/loongarch_ipi.c | 44 ++++++++++++++++++++++++++++++++++------- hw/loongarch/virt.c | 1 + target/loongarch/cpu.h | 2 ++ 3 files changed, 40 insertions(+), 7 deletions(-) diff --git a/hw/intc/loongarch_ipi.c b/hw/intc/loongarch_ipi.c index d6ab91721e..e5f396ca75 100644 --- a/hw/intc/loongarch_ipi.c +++ b/hw/intc/loongarch_ipi.c @@ -17,6 +17,8 @@ #include "target/loongarch/internals.h" #include "trace.h" +static void loongarch_ipi_writel(void *, hwaddr, uint64_t, unsigned); + static uint64_t loongarch_ipi_readl(void *opaque, hwaddr addr, unsigned size) { IPICore *s = opaque; @@ -75,13 +77,42 @@ static void send_ipi_data(CPULoongArchState *env, uint64_t val, hwaddr addr) data, MEMTXATTRS_UNSPECIFIED, NULL); } +static int archid_cmp(const void *a, const void *b) +{ + CPUArchId *archid_a = (CPUArchId *)a; + CPUArchId *archid_b = (CPUArchId *)b; + + return archid_a->arch_id - archid_b->arch_id; +} + +static CPUArchId *find_cpu_by_archid(MachineState *ms, uint32_t id) +{ + CPUArchId apic_id, *found_cpu; + + apic_id.arch_id = id; + found_cpu = bsearch(&apic_id, ms->possible_cpus->cpus, + ms->possible_cpus->len, sizeof(*ms->possible_cpus->cpus), + archid_cmp); + + return found_cpu; +} + +static CPUState *ipi_getcpu(int arch_id) +{ + MachineState *machine = MACHINE(qdev_get_machine()); + CPUArchId *archid; + + archid = find_cpu_by_archid(machine, arch_id); + return CPU(archid->cpu); +} + static void ipi_send(uint64_t val) { uint32_t cpuid; uint8_t vector; - CPULoongArchState *env; CPUState *cs; LoongArchCPU *cpu; + LoongArchIPI *s; cpuid = extract32(val, 16, 10); if (cpuid >= LOONGARCH_MAX_CPUS) { @@ -92,11 +123,10 @@ static void ipi_send(uint64_t val) /* IPI status vector */ vector = extract8(val, 0, 5); - cs = qemu_get_cpu(cpuid); + cs = ipi_getcpu(cpuid); cpu = LOONGARCH_CPU(cs); - env = &cpu->env; - address_space_stl(&env->address_space_iocsr, 0x1008, - BIT(vector), MEMTXATTRS_UNSPECIFIED, NULL); + s = LOONGARCH_IPI(cpu->env.ipistate); + loongarch_ipi_writel(&s->ipi_core, CORE_SET_OFF, BIT(vector), 4); } static void mail_send(uint64_t val) @@ -114,7 +144,7 @@ static void mail_send(uint64_t val) } addr = 0x1020 + (val & 0x1c); - cs = qemu_get_cpu(cpuid); + cs = ipi_getcpu(cpuid); cpu = LOONGARCH_CPU(cs); env = &cpu->env; send_ipi_data(env, val, addr); @@ -135,7 +165,7 @@ static void any_send(uint64_t val) } addr = val & 0xffff; - cs = qemu_get_cpu(cpuid); + cs = ipi_getcpu(cpuid); cpu = LOONGARCH_CPU(cs); env = &cpu->env; send_ipi_data(env, val, addr); diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 83c1e43ff5..6e1c42fb2b 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -616,6 +616,7 @@ static void loongarch_irq_init(LoongArchMachineState *lams) memory_region_add_subregion(&env->system_iocsr, APIC_BASE, sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), cpu)); + env->ipistate = ipi; } /* diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 1f37e36b7c..b23f38c3d5 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -351,6 +351,8 @@ typedef struct CPUArchState { MemoryRegion iocsr_mem; bool load_elf; uint64_t elf_address; + /* Store ipistate to access from this struct */ + DeviceState *ipistate; #endif } CPULoongArchState; -- 2.39.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v1 0/2] Add LoongArch cpu arch_id support 2023-05-18 1:41 [PATCH v1 0/2] Add LoongArch cpu arch_id support Song Gao 2023-05-18 1:41 ` [PATCH v1 1/2] hw/loongarch/virt: Add " Song Gao 2023-05-18 1:41 ` [PATCH v1 2/2] hw/intc: Set physical cpuid route for LoongArch ipi device Song Gao @ 2023-05-30 8:40 ` Song Gao 2 siblings, 0 replies; 6+ messages in thread From: Song Gao @ 2023-05-30 8:40 UTC (permalink / raw) To: qemu-devel Cc: richard.henderson, peter.maydell, philmd, imammedo, anisinha, mst, alex.bennee, maobibo, yangxiaojuan, Tianrui Zhao, Jiaxun Yang ping~ 在 2023/5/18 上午9:41, Song Gao 写道: > 1 Add LoongArch cpu arch_id support; > 2 Fill Acpi table with arch_id; > 3 set physical cpuid route for LoongArch ipi device. > > Song Gao (2): > hw/loongarch/virt: Add cpu arch_id support > hw/intc: Set physical cpuid route for LoongArch ipi device > > hw/intc/loongarch_ipi.c | 44 ++++++++++++++++++++++++++++++++------- > hw/loongarch/acpi-build.c | 20 ++++++++++++------ > hw/loongarch/virt.c | 35 +++++++++++++++++++++++++++++-- > target/loongarch/cpu.h | 2 ++ > 4 files changed, 86 insertions(+), 15 deletions(-) > ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-05-30 12:24 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-05-18 1:41 [PATCH v1 0/2] Add LoongArch cpu arch_id support Song Gao 2023-05-18 1:41 ` [PATCH v1 1/2] hw/loongarch/virt: Add " Song Gao 2023-05-30 11:53 ` Tianrui Zhao 2023-05-30 12:23 ` Song Gao 2023-05-18 1:41 ` [PATCH v1 2/2] hw/intc: Set physical cpuid route for LoongArch ipi device Song Gao 2023-05-30 8:40 ` [PATCH v1 0/2] Add LoongArch cpu arch_id support Song Gao
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