From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [PATCH 9/9] util: Add cpuinfo-aarch64.c
Date: Wed, 17 May 2023 21:40:58 -0700 [thread overview]
Message-ID: <20230518044058.2777467-10-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230518044058.2777467-1-richard.henderson@linaro.org>
Move the code from tcg/. The only use of these bits so far
is with respect to the atomicity of tcg operations.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/host/aarch64/cpuinfo.h | 22 +++++++++++
tcg/aarch64/tcg-target.h | 4 +-
util/cpuinfo-aarch64.c | 67 ++++++++++++++++++++++++++++++++++
tcg/aarch64/tcg-target.c.inc | 41 +--------------------
util/meson.build | 4 +-
5 files changed, 95 insertions(+), 43 deletions(-)
create mode 100644 include/host/aarch64/cpuinfo.h
create mode 100644 util/cpuinfo-aarch64.c
diff --git a/include/host/aarch64/cpuinfo.h b/include/host/aarch64/cpuinfo.h
new file mode 100644
index 0000000000..82227890b4
--- /dev/null
+++ b/include/host/aarch64/cpuinfo.h
@@ -0,0 +1,22 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ * Host specific cpu indentification for AArch64.
+ */
+
+#ifndef HOST_CPUINFO_H
+#define HOST_CPUINFO_H
+
+#define CPUINFO_ALWAYS (1u << 0) /* so cpuinfo is nonzero */
+#define CPUINFO_LSE (1u << 1)
+#define CPUINFO_LSE2 (1u << 2)
+
+/* Initialized with a constructor. */
+extern unsigned cpuinfo;
+
+/*
+ * We cannot rely on constructor ordering, so other constructors must
+ * use the function interface rather than the variable above.
+ */
+unsigned cpuinfo_init(void);
+
+#endif /* HOST_CPUINFO_H */
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 74ee2ed255..b6ff440e15 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -57,8 +57,8 @@ typedef enum {
#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN
#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL
-extern bool have_lse;
-extern bool have_lse2;
+#define have_lse (cpuinfo & CPUINFO_LSE)
+#define have_lse2 (cpuinfo & CPUINFO_LSE2)
/* optional instructions */
#define TCG_TARGET_HAS_div_i32 1
diff --git a/util/cpuinfo-aarch64.c b/util/cpuinfo-aarch64.c
new file mode 100644
index 0000000000..a774fb170f
--- /dev/null
+++ b/util/cpuinfo-aarch64.c
@@ -0,0 +1,67 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ * Host specific cpu indentification for AArch64.
+ */
+
+#include "qemu/osdep.h"
+#include "cpuinfo.h"
+
+#ifdef CONFIG_LINUX
+# ifdef CONFIG_GETAUXVAL
+# include <sys/auxv.h>
+# else
+# include <asm/hwcap.h>
+# include "elf.h"
+# endif
+#endif
+#ifdef CONFIG_DARWIN
+# include <sys/sysctl.h>
+#endif
+
+unsigned cpuinfo;
+
+#ifdef CONFIG_DARWIN
+static bool sysctl_for_bool(const char *name)
+{
+ int val = 0;
+ size_t len = sizeof(val);
+
+ if (sysctlbyname(name, &val, &len, NULL, 0) == 0) {
+ return val != 0;
+ }
+
+ /*
+ * We might in the future ask for properties not present in older kernels,
+ * but we're only asking about static properties, all of which should be
+ * 'int'. So we shouln't see ENOMEM (val too small), or any of the other
+ * more exotic errors.
+ */
+ assert(errno == ENOENT);
+ return false;
+}
+#endif
+
+/* Called both as constructor and (possibly) via other constructors. */
+unsigned __attribute__((constructor)) cpuinfo_init(void)
+{
+ unsigned info = cpuinfo;
+
+ if (info) {
+ return info;
+ }
+
+ info = CPUINFO_ALWAYS;
+
+#ifdef CONFIG_LINUX
+ unsigned long hwcap = qemu_getauxval(AT_HWCAP);
+ info |= (hwcap & HWCAP_ATOMICS ? CPUINFO_LSE : 0);
+ info |= (hwcap & HWCAP_USCAT ? CPUINFO_LSE2 : 0);
+#endif
+#ifdef CONFIG_DARWIN
+ info |= sysctl_for_bool("hw.optional.arm.FEAT_LSE") * CPUINFO_LSE;
+ info |= sysctl_for_bool("hw.optional.arm.FEAT_LSE2") * CPUINFO_LSE2;
+#endif
+
+ cpuinfo = info;
+ return info;
+}
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index bc6b99a1bd..1e5ffb7a49 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -13,12 +13,7 @@
#include "../tcg-ldst.c.inc"
#include "../tcg-pool.c.inc"
#include "qemu/bitops.h"
-#ifdef __linux__
-#include <asm/hwcap.h>
-#endif
-#ifdef CONFIG_DARWIN
-#include <sys/sysctl.h>
-#endif
+#include "cpuinfo.h"
/* We're going to re-use TCGType in setting of the SF bit, which controls
the size of the operation performed. If we know the values match, it
@@ -77,9 +72,6 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
return TCG_REG_X0 + slot;
}
-bool have_lse;
-bool have_lse2;
-
#define TCG_REG_TMP TCG_REG_X30
#define TCG_VEC_TMP TCG_REG_V31
@@ -2878,39 +2870,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
}
}
-#ifdef CONFIG_DARWIN
-static bool sysctl_for_bool(const char *name)
-{
- int val = 0;
- size_t len = sizeof(val);
-
- if (sysctlbyname(name, &val, &len, NULL, 0) == 0) {
- return val != 0;
- }
-
- /*
- * We might in the future ask for properties not present in older kernels,
- * but we're only asking about static properties, all of which should be
- * 'int'. So we shouln't see ENOMEM (val too small), or any of the other
- * more exotic errors.
- */
- assert(errno == ENOENT);
- return false;
-}
-#endif
-
static void tcg_target_init(TCGContext *s)
{
-#ifdef __linux__
- unsigned long hwcap = qemu_getauxval(AT_HWCAP);
- have_lse = hwcap & HWCAP_ATOMICS;
- have_lse2 = hwcap & HWCAP_USCAT;
-#endif
-#ifdef CONFIG_DARWIN
- have_lse = sysctl_for_bool("hw.optional.arm.FEAT_LSE");
- have_lse2 = sysctl_for_bool("hw.optional.arm.FEAT_LSE2");
-#endif
-
tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffffu;
tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffffu;
tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
diff --git a/util/meson.build b/util/meson.build
index 714c783b4c..c43b910aa7 100644
--- a/util/meson.build
+++ b/util/meson.build
@@ -107,6 +107,8 @@ if have_block
util_ss.add(when: 'CONFIG_LINUX', if_true: files('vfio-helpers.c'))
endif
-if cpu in ['x86', 'x86_64']
+if cpu == 'aarch64'
+ util_ss.add(files('cpuinfo-aarch64.c'))
+elif cpu in ['x86', 'x86_64']
util_ss.add(files('cpuinfo-i386.c'))
endif
--
2.34.1
next prev parent reply other threads:[~2023-05-18 4:42 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-18 4:40 [PATCH 0/9] Host-specific includes, begin cpuinfo.h Richard Henderson
2023-05-18 4:40 ` [PATCH 1/9] util: Introduce host-specific cpuinfo.h Richard Henderson
2023-05-18 9:30 ` Juan Quintela
2023-05-18 4:40 ` [PATCH 2/9] util: Add cpuinfo-i386.c Richard Henderson
2023-05-18 9:35 ` Juan Quintela
2023-05-18 12:45 ` Richard Henderson
2023-05-18 4:40 ` [PATCH 3/9] util: Add i386 CPUINFO_ATOMIC_VMOVDQU Richard Henderson
2023-05-18 15:52 ` Peter Maydell
2023-05-18 4:40 ` [PATCH 4/9] tcg/i386: Use cpuinfo.h Richard Henderson
2023-05-18 15:53 ` Peter Maydell
2023-05-18 4:40 ` [PATCH 5/9] util/bufferiszero: Use i386 cpuinfo.h Richard Henderson
2023-05-18 9:49 ` Juan Quintela
2023-05-18 12:48 ` Richard Henderson
2023-05-18 4:40 ` [PATCH 6/9] migration/xbzrle: Shuffle function order Richard Henderson
2023-05-18 9:19 ` Juan Quintela
2023-05-18 4:40 ` [PATCH 7/9] migration/xbzrle: Use i386 cacheinfo.h Richard Henderson
2023-05-18 9:44 ` Juan Quintela
2023-05-18 4:40 ` [PATCH 8/9] migration: Build migration_files once Richard Henderson
2023-05-18 9:20 ` Juan Quintela
2023-05-18 4:40 ` Richard Henderson [this message]
2023-05-18 15:55 ` [PATCH 9/9] util: Add cpuinfo-aarch64.c Peter Maydell
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