From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: Ira Weiny <ira.weiny@intel.com>
Cc: <qemu-devel@nongnu.org>, <linux-cxl@vger.kernel.org>,
Dave Jiang <dave.jiang@intel.com>,
Dan Williams <dan.j.williams@intel.com>
Subject: Re: [PATCH RFC 1/5] hw/cxl: Use define for build bug detection
Date: Thu, 18 May 2023 10:54:16 +0100 [thread overview]
Message-ID: <20230518105416.000054c9@Huawei.com> (raw)
In-Reply-To: <20230517-rfc-type2-dev-v1-1-6eb2e470981b@intel.com>
On Wed, 17 May 2023 19:45:54 -0700
Ira Weiny <ira.weiny@intel.com> wrote:
> Magic numbers can be confusing.
>
> Use the range size define for CXL.cachemem rather than a magic number.
> Update/add spec references.
>
> Signed-off-by: Ira Weiny <ira.weiny@intel.com>
I guess we should do a scrub to move all refs to 3.0 soon
given it's horrible having a mixture of spec versions for the references.
For future specs, we should only do this when sufficient X.Y references
have started to appear - I think that's true for r3.0 now.
Jonathan
> ---
> include/hw/cxl/cxl_component.h | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h
> index 52b6a2d67f40..bca2b756c202 100644
> --- a/include/hw/cxl/cxl_component.h
> +++ b/include/hw/cxl/cxl_component.h
> @@ -10,7 +10,7 @@
> #ifndef CXL_COMPONENT_H
> #define CXL_COMPONENT_H
>
> -/* CXL 2.0 - 8.2.4 */
> +/* CXL 3.0 - 8.2.3 */
> #define CXL2_COMPONENT_IO_REGION_SIZE 0x1000
> #define CXL2_COMPONENT_CM_REGION_SIZE 0x1000
> #define CXL2_COMPONENT_BLOCK_SIZE 0x10000
> @@ -173,7 +173,9 @@ HDM_DECODER_INIT(3);
> (CXL_IDE_REGISTERS_OFFSET + CXL_IDE_REGISTERS_SIZE)
> #define CXL_SNOOP_REGISTERS_SIZE 0x8
>
> -QEMU_BUILD_BUG_MSG((CXL_SNOOP_REGISTERS_OFFSET + CXL_SNOOP_REGISTERS_SIZE) >= 0x1000,
> +/* CXL 3.0 8.2.3 Table 8-21 */
> +QEMU_BUILD_BUG_MSG((CXL_SNOOP_REGISTERS_OFFSET +
> + CXL_SNOOP_REGISTERS_SIZE) >= CXL2_COMPONENT_CM_REGION_SIZE,
> "No space for registers");
>
> typedef struct component_registers {
>
next prev parent reply other threads:[~2023-05-18 9:54 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-18 2:45 [PATCH RFC 0/5] hw/cxl: Type 2 Device RFC Ira Weiny
2023-05-18 2:45 ` [PATCH RFC 1/5] hw/cxl: Use define for build bug detection Ira Weiny
2023-05-18 9:54 ` Jonathan Cameron via [this message]
2023-05-18 20:19 ` Ira Weiny
2023-05-19 15:14 ` Jonathan Cameron via
2023-05-23 14:18 ` Ira Weiny
2023-05-18 2:45 ` [PATCH RFC 2/5] hw/cxl: Refactor component register initialization Ira Weiny
2023-05-18 2:45 ` [PATCH RFC 3/5] hw/cxl: Derive a CXL accelerator device from Type-3 Ira Weiny
2023-05-18 2:45 ` [PATCH RFC 4/5] hw/cxl/accel: Add Back-Invalidate decoder capbility structure Ira Weiny
2023-05-18 2:45 ` [PATCH RFC 5/5] hw/cxl: Add UIO HDM decoder register fields Ira Weiny
2024-10-17 16:57 ` [PATCH RFC 0/5] hw/cxl: Type 2 Device RFC Cédric Le Goater
2024-10-18 14:49 ` Zhi Wang
2024-10-18 15:25 ` Alejandro Lucero Palau
2024-10-18 16:19 ` Jonathan Cameron via
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