From: Taylor Simpson <tsimpson@quicinc.com>
To: qemu-devel@nongnu.org
Cc: tsimpson@quicinc.com, richard.henderson@linaro.org,
philmd@linaro.org, peter.maydell@linaro.org, bcain@quicinc.com,
quic_mathbern@quicinc.com, stefanha@redhat.com, ale@rev.ng,
anjo@rev.ng, quic_mliebel@quicinc.com
Subject: [PULL v2 07/44] Hexagon (tests/tcg/hexagon) Add v69 HVX tests
Date: Thu, 18 May 2023 13:03:34 -0700 [thread overview]
Message-ID: <20230518200411.271148-8-tsimpson@quicinc.com> (raw)
In-Reply-To: <20230518200411.271148-1-tsimpson@quicinc.com>
The following instructions are tested
V6_vasrvuhubrndsat
V6_vasrvuhubsat
V6_vasrvwuhrndsat
V6_vasrvwuhsat
V6_vassign_tmp
V6_vcombine_tmp
V6_vmpyuhvs
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230427224057.3766963-8-tsimpson@quicinc.com>
---
tests/tcg/hexagon/v69_hvx.c | 318 ++++++++++++++++++++++++++++++
tests/tcg/hexagon/Makefile.target | 3 +
2 files changed, 321 insertions(+)
create mode 100644 tests/tcg/hexagon/v69_hvx.c
diff --git a/tests/tcg/hexagon/v69_hvx.c b/tests/tcg/hexagon/v69_hvx.c
new file mode 100644
index 0000000000..a0d567d142
--- /dev/null
+++ b/tests/tcg/hexagon/v69_hvx.c
@@ -0,0 +1,318 @@
+/*
+ * Copyright(c) 2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <string.h>
+#include <limits.h>
+
+int err;
+
+#include "hvx_misc.h"
+
+#define fVROUND(VAL, SHAMT) \
+ ((VAL) + (((SHAMT) > 0) ? (1LL << ((SHAMT) - 1)) : 0))
+
+#define fVSATUB(VAL) \
+ ((((VAL) & 0xffLL) == (VAL)) ? \
+ (VAL) : \
+ ((((int32_t)(VAL)) < 0) ? 0 : 0xff))
+
+#define fVSATUH(VAL) \
+ ((((VAL) & 0xffffLL) == (VAL)) ? \
+ (VAL) : \
+ ((((int32_t)(VAL)) < 0) ? 0 : 0xffff))
+
+static void test_vasrvuhubrndsat(void)
+{
+ void *p0 = buffer0;
+ void *p1 = buffer1;
+ void *pout = output;
+
+ memset(expect, 0xaa, sizeof(expect));
+ memset(output, 0xbb, sizeof(output));
+
+ for (int i = 0; i < BUFSIZE / 2; i++) {
+ asm("v4 = vmem(%0 + #0)\n\t"
+ "v5 = vmem(%0 + #1)\n\t"
+ "v6 = vmem(%1 + #0)\n\t"
+ "v5.ub = vasr(v5:4.uh, v6.ub):rnd:sat\n\t"
+ "vmem(%2) = v5\n\t"
+ : : "r"(p0), "r"(p1), "r"(pout)
+ : "v4", "v5", "v6", "memory");
+ p0 += sizeof(MMVector) * 2;
+ p1 += sizeof(MMVector);
+ pout += sizeof(MMVector);
+
+ for (int j = 0; j < MAX_VEC_SIZE_BYTES / 2; j++) {
+ int shamt;
+ uint8_t byte0;
+ uint8_t byte1;
+
+ shamt = buffer1[i].ub[2 * j + 0] & 0x7;
+ byte0 = fVSATUB(fVROUND(buffer0[2 * i + 0].uh[j], shamt) >> shamt);
+ shamt = buffer1[i].ub[2 * j + 1] & 0x7;
+ byte1 = fVSATUB(fVROUND(buffer0[2 * i + 1].uh[j], shamt) >> shamt);
+ expect[i].uh[j] = (byte1 << 8) | (byte0 & 0xff);
+ }
+ }
+
+ check_output_h(__LINE__, BUFSIZE / 2);
+}
+
+static void test_vasrvuhubsat(void)
+{
+ void *p0 = buffer0;
+ void *p1 = buffer1;
+ void *pout = output;
+
+ memset(expect, 0xaa, sizeof(expect));
+ memset(output, 0xbb, sizeof(output));
+
+ for (int i = 0; i < BUFSIZE / 2; i++) {
+ asm("v4 = vmem(%0 + #0)\n\t"
+ "v5 = vmem(%0 + #1)\n\t"
+ "v6 = vmem(%1 + #0)\n\t"
+ "v5.ub = vasr(v5:4.uh, v6.ub):sat\n\t"
+ "vmem(%2) = v5\n\t"
+ : : "r"(p0), "r"(p1), "r"(pout)
+ : "v4", "v5", "v6", "memory");
+ p0 += sizeof(MMVector) * 2;
+ p1 += sizeof(MMVector);
+ pout += sizeof(MMVector);
+
+ for (int j = 0; j < MAX_VEC_SIZE_BYTES / 2; j++) {
+ int shamt;
+ uint8_t byte0;
+ uint8_t byte1;
+
+ shamt = buffer1[i].ub[2 * j + 0] & 0x7;
+ byte0 = fVSATUB(buffer0[2 * i + 0].uh[j] >> shamt);
+ shamt = buffer1[i].ub[2 * j + 1] & 0x7;
+ byte1 = fVSATUB(buffer0[2 * i + 1].uh[j] >> shamt);
+ expect[i].uh[j] = (byte1 << 8) | (byte0 & 0xff);
+ }
+ }
+
+ check_output_h(__LINE__, BUFSIZE / 2);
+}
+
+static void test_vasrvwuhrndsat(void)
+{
+ void *p0 = buffer0;
+ void *p1 = buffer1;
+ void *pout = output;
+
+ memset(expect, 0xaa, sizeof(expect));
+ memset(output, 0xbb, sizeof(output));
+
+ for (int i = 0; i < BUFSIZE / 2; i++) {
+ asm("v4 = vmem(%0 + #0)\n\t"
+ "v5 = vmem(%0 + #1)\n\t"
+ "v6 = vmem(%1 + #0)\n\t"
+ "v5.uh = vasr(v5:4.w, v6.uh):rnd:sat\n\t"
+ "vmem(%2) = v5\n\t"
+ : : "r"(p0), "r"(p1), "r"(pout)
+ : "v4", "v5", "v6", "memory");
+ p0 += sizeof(MMVector) * 2;
+ p1 += sizeof(MMVector);
+ pout += sizeof(MMVector);
+
+ for (int j = 0; j < MAX_VEC_SIZE_BYTES / 4; j++) {
+ int shamt;
+ uint16_t half0;
+ uint16_t half1;
+
+ shamt = buffer1[i].uh[2 * j + 0] & 0xf;
+ half0 = fVSATUH(fVROUND(buffer0[2 * i + 0].w[j], shamt) >> shamt);
+ shamt = buffer1[i].uh[2 * j + 1] & 0xf;
+ half1 = fVSATUH(fVROUND(buffer0[2 * i + 1].w[j], shamt) >> shamt);
+ expect[i].w[j] = (half1 << 16) | (half0 & 0xffff);
+ }
+ }
+
+ check_output_w(__LINE__, BUFSIZE / 2);
+}
+
+static void test_vasrvwuhsat(void)
+{
+ void *p0 = buffer0;
+ void *p1 = buffer1;
+ void *pout = output;
+
+ memset(expect, 0xaa, sizeof(expect));
+ memset(output, 0xbb, sizeof(output));
+
+ for (int i = 0; i < BUFSIZE / 2; i++) {
+ asm("v4 = vmem(%0 + #0)\n\t"
+ "v5 = vmem(%0 + #1)\n\t"
+ "v6 = vmem(%1 + #0)\n\t"
+ "v5.uh = vasr(v5:4.w, v6.uh):sat\n\t"
+ "vmem(%2) = v5\n\t"
+ : : "r"(p0), "r"(p1), "r"(pout)
+ : "v4", "v5", "v6", "memory");
+ p0 += sizeof(MMVector) * 2;
+ p1 += sizeof(MMVector);
+ pout += sizeof(MMVector);
+
+ for (int j = 0; j < MAX_VEC_SIZE_BYTES / 4; j++) {
+ int shamt;
+ uint16_t half0;
+ uint16_t half1;
+
+ shamt = buffer1[i].uh[2 * j + 0] & 0xf;
+ half0 = fVSATUH(buffer0[2 * i + 0].w[j] >> shamt);
+ shamt = buffer1[i].uh[2 * j + 1] & 0xf;
+ half1 = fVSATUH(buffer0[2 * i + 1].w[j] >> shamt);
+ expect[i].w[j] = (half1 << 16) | (half0 & 0xffff);
+ }
+ }
+
+ check_output_w(__LINE__, BUFSIZE / 2);
+}
+
+static void test_vassign_tmp(void)
+{
+ void *p0 = buffer0;
+ void *pout = output;
+
+ memset(expect, 0xaa, sizeof(expect));
+ memset(output, 0xbb, sizeof(output));
+
+ for (int i = 0; i < BUFSIZE; i++) {
+ /*
+ * Assign into v12 as .tmp, then use it in the next packet
+ * Should get the new value within the same packet and
+ * the old value in the next packet
+ */
+ asm("v3 = vmem(%0 + #0)\n\t"
+ "r1 = #1\n\t"
+ "v12 = vsplat(r1)\n\t"
+ "r1 = #2\n\t"
+ "v13 = vsplat(r1)\n\t"
+ "{\n\t"
+ " v12.tmp = v13\n\t"
+ " v4.w = vadd(v12.w, v3.w)\n\t"
+ "}\n\t"
+ "v4.w = vadd(v4.w, v12.w)\n\t"
+ "vmem(%1 + #0) = v4\n\t"
+ : : "r"(p0), "r"(pout)
+ : "r1", "v3", "v4", "v12", "v13", "memory");
+ p0 += sizeof(MMVector);
+ pout += sizeof(MMVector);
+
+ for (int j = 0; j < MAX_VEC_SIZE_BYTES / 4; j++) {
+ expect[i].w[j] = buffer0[i].w[j] + 3;
+ }
+ }
+
+ check_output_w(__LINE__, BUFSIZE);
+}
+
+static void test_vcombine_tmp(void)
+{
+ void *p0 = buffer0;
+ void *p1 = buffer1;
+ void *pout = output;
+
+ memset(expect, 0xaa, sizeof(expect));
+ memset(output, 0xbb, sizeof(output));
+
+ for (int i = 0; i < BUFSIZE; i++) {
+ /*
+ * Combine into v13:12 as .tmp, then use it in the next packet
+ * Should get the new value within the same packet and
+ * the old value in the next packet
+ */
+ asm("v3 = vmem(%0 + #0)\n\t"
+ "r1 = #1\n\t"
+ "v12 = vsplat(r1)\n\t"
+ "r1 = #2\n\t"
+ "v13 = vsplat(r1)\n\t"
+ "r1 = #3\n\t"
+ "v14 = vsplat(r1)\n\t"
+ "r1 = #4\n\t"
+ "v15 = vsplat(r1)\n\t"
+ "{\n\t"
+ " v13:12.tmp = vcombine(v15, v14)\n\t"
+ " v4.w = vadd(v12.w, v3.w)\n\t"
+ " v16 = v13\n\t"
+ "}\n\t"
+ "v4.w = vadd(v4.w, v12.w)\n\t"
+ "v4.w = vadd(v4.w, v13.w)\n\t"
+ "v4.w = vadd(v4.w, v16.w)\n\t"
+ "vmem(%2 + #0) = v4\n\t"
+ : : "r"(p0), "r"(p1), "r"(pout)
+ : "r1", "v3", "v4", "v12", "v13", "v14", "v15", "v16", "memory");
+ p0 += sizeof(MMVector);
+ p1 += sizeof(MMVector);
+ pout += sizeof(MMVector);
+
+ for (int j = 0; j < MAX_VEC_SIZE_BYTES / 4; j++) {
+ expect[i].w[j] = buffer0[i].w[j] + 10;
+ }
+ }
+
+ check_output_w(__LINE__, BUFSIZE);
+}
+
+static void test_vmpyuhvs(void)
+{
+ void *p0 = buffer0;
+ void *p1 = buffer1;
+ void *pout = output;
+
+ memset(expect, 0xaa, sizeof(expect));
+ memset(output, 0xbb, sizeof(output));
+
+ for (int i = 0; i < BUFSIZE; i++) {
+ asm("v4 = vmem(%0 + #0)\n\t"
+ "v5 = vmem(%1 + #0)\n\t"
+ "v4.uh = vmpy(V4.uh, v5.uh):>>16\n\t"
+ "vmem(%2) = v4\n\t"
+ : : "r"(p0), "r"(p1), "r"(pout)
+ : "v4", "v5", "memory");
+ p0 += sizeof(MMVector);
+ p1 += sizeof(MMVector);
+ pout += sizeof(MMVector);
+
+ for (int j = 0; j < MAX_VEC_SIZE_BYTES / 2; j++) {
+ expect[i].uh[j] = (buffer0[i].uh[j] * buffer1[i].uh[j]) >> 16;
+ }
+ }
+
+ check_output_h(__LINE__, BUFSIZE);
+}
+
+int main()
+{
+ init_buffers();
+
+ test_vasrvuhubrndsat();
+ test_vasrvuhubsat();
+ test_vasrvwuhrndsat();
+ test_vasrvwuhsat();
+
+ test_vassign_tmp();
+ test_vcombine_tmp();
+
+ test_vmpyuhvs();
+
+ puts(err ? "FAIL" : "PASS");
+ return err ? 1 : 0;
+}
diff --git a/tests/tcg/hexagon/Makefile.target b/tests/tcg/hexagon/Makefile.target
index 2ee930cf1f..558c056148 100644
--- a/tests/tcg/hexagon/Makefile.target
+++ b/tests/tcg/hexagon/Makefile.target
@@ -78,6 +78,7 @@ HEX_TESTS += test_vspliceb
HEX_TESTS += v68_scalar
HEX_TESTS += v68_hvx
+HEX_TESTS += v69_hvx
TESTS += $(HEX_TESTS)
@@ -95,6 +96,8 @@ hvx_misc: CFLAGS += -mhvx
hvx_histogram: CFLAGS += -mhvx -Wno-gnu-folding-constant
v68_hvx: v68_hvx.c hvx_misc.h v6mpy_ref.c.inc
v68_hvx: CFLAGS += -mhvx -Wno-unused-function
+v69_hvx: v69_hvx.c hvx_misc.h
+v69_hvx: CFLAGS += -mhvx -Wno-unused-function
hvx_histogram: hvx_histogram.c hvx_histogram_row.S
$(CC) $(CFLAGS) $(CROSS_CC_GUEST_CFLAGS) $^ -o $@ $(LDFLAGS)
--
2.25.1
next prev parent reply other threads:[~2023-05-18 20:09 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-18 20:03 [PULL v2 00/44] Hexagon update Taylor Simpson
2023-05-18 20:03 ` [PULL v2 01/44] Hexagon (target/hexagon) Add support for v68/v69/v71/v73 Taylor Simpson
2023-05-18 20:03 ` [PULL v2 02/44] Hexagon (target/hexagon) Add v68 scalar instructions Taylor Simpson
2023-05-18 20:03 ` [PULL v2 03/44] Hexagon (tests/tcg/hexagon) Add v68 scalar tests Taylor Simpson
2023-05-18 20:03 ` [PULL v2 04/44] Hexagon (target/hexagon) Add v68 HVX instructions Taylor Simpson
2023-05-18 20:03 ` [PULL v2 05/44] Hexagon (tests/tcg/hexagon) Add v68 HVX tests Taylor Simpson
2023-05-18 20:03 ` [PULL v2 06/44] Hexagon (target/hexagon) Add v69 HVX instructions Taylor Simpson
2023-05-18 20:03 ` Taylor Simpson [this message]
2023-05-18 20:03 ` [PULL v2 08/44] Hexagon (target/hexagon) Add v73 scalar instructions Taylor Simpson
2023-05-18 20:03 ` [PULL v2 09/44] Hexagon (tests/tcg/hexagon) Add v73 scalar tests Taylor Simpson
2023-05-18 20:03 ` [PULL v2 10/44] meson.build Add CONFIG_HEXAGON_IDEF_PARSER Taylor Simpson
2023-05-18 20:03 ` [PULL v2 11/44] Hexagon (target/hexagon) Add DisasContext arg to gen_log_reg_write Taylor Simpson
2023-05-18 20:03 ` [PULL v2 12/44] Hexagon (target/hexagon) Add overrides for loop setup instructions Taylor Simpson
2023-05-18 20:03 ` [PULL v2 13/44] Hexagon (target/hexagon) Add overrides for allocframe/deallocframe Taylor Simpson
2023-05-18 20:03 ` [PULL v2 14/44] Hexagon (target/hexagon) Add overrides for clr[tf]new Taylor Simpson
2023-05-18 20:03 ` [PULL v2 15/44] Hexagon (target/hexagon) Remove log_reg_write from op_helper.[ch] Taylor Simpson
2023-05-18 20:03 ` [PULL v2 16/44] Hexagon (target/hexagon) Eliminate uses of log_pred_write function Taylor Simpson
2023-05-18 20:03 ` [PULL v2 17/44] Hexagon (target/hexagon) Clean up pred_written usage Taylor Simpson
2023-05-18 20:03 ` [PULL v2 18/44] Hexagon (target/hexagon) Don't overlap dest writes with source reads Taylor Simpson
2023-05-18 20:03 ` [PULL v2 19/44] Hexagon (target/hexagon) Mark registers as read during packet analysis Taylor Simpson
2023-05-18 20:03 ` [PULL v2 20/44] Hexagon (target/hexagon) Short-circuit packet register writes Taylor Simpson
2023-05-18 20:03 ` [PULL v2 21/44] Hexagon (target/hexagon) Short-circuit packet predicate writes Taylor Simpson
2023-05-18 20:03 ` [PULL v2 22/44] Hexagon (target/hexagon) Short-circuit packet HVX writes Taylor Simpson
2023-05-18 20:03 ` [PULL v2 23/44] Hexagon (target/hexagon) Short-circuit more HVX single instruction packets Taylor Simpson
2023-05-18 20:03 ` [PULL v2 24/44] Hexagon (target/hexagon) Add overrides for disabled idef-parser insns Taylor Simpson
2023-05-18 20:03 ` [PULL v2 25/44] Hexagon (target/hexagon) Make special new_value for USR Taylor Simpson
2023-05-18 20:03 ` [PULL v2 26/44] Hexagon (target/hexagon) Move new_value to DisasContext Taylor Simpson
2023-05-18 20:03 ` [PULL v2 27/44] Hexagon (target/hexagon) Move new_pred_value " Taylor Simpson
2023-05-18 20:03 ` [PULL v2 28/44] Hexagon (target/hexagon) Move pred_written " Taylor Simpson
2023-05-18 20:03 ` [PULL v2 29/44] Hexagon (target/hexagon) Move pkt_has_store_s1 " Taylor Simpson
2023-05-18 20:03 ` [PULL v2 30/44] Hexagon (target/hexagon) Move items " Taylor Simpson
2023-05-18 20:03 ` [PULL v2 31/44] Hexagon (target/hexagon) Additional instructions handled by idef-parser Taylor Simpson
2023-05-18 20:03 ` [PULL v2 32/44] target/hexagon: fix = vs. == mishap Taylor Simpson
2023-05-18 20:04 ` [PULL v2 33/44] Hexagon (target/hexagon/*.py): raise exception on reg parsing error Taylor Simpson
2023-05-18 20:04 ` [PULL v2 34/44] Hexagon: list available CPUs with `-cpu help` Taylor Simpson
2023-05-18 20:04 ` [PULL v2 35/44] Hexagon: append eflags to unknown cpu model string Taylor Simpson
2023-05-18 20:04 ` [PULL v2 36/44] Hexagon (iclass): update J4_hintjumpr slot constraints Taylor Simpson
2023-05-18 20:04 ` [PULL v2 37/44] Hexagon (decode): look for pkts with multiple insns at the same slot Taylor Simpson
2023-05-18 20:04 ` [PULL v2 38/44] Remove test_vshuff from hvx_misc tests Taylor Simpson
2023-05-18 20:04 ` [PULL v2 39/44] gdbstub: only send stop-reply packets when allowed to Taylor Simpson
2023-05-18 20:04 ` [PULL v2 40/44] gdbstub: add test for untimely stop-reply packets Taylor Simpson
2023-08-04 14:57 ` Richard Henderson
2023-08-07 13:01 ` Matheus Tavares Bernardino
2023-05-18 20:04 ` [PULL v2 41/44] Hexagon: add core gdbstub xml data for LLDB Taylor Simpson
2023-05-18 20:04 ` [PULL v2 42/44] Hexagon (gdbstub): fix p3:0 read and write via stub Taylor Simpson
2023-05-18 20:04 ` [PULL v2 43/44] Hexagon (gdbstub): add HVX support Taylor Simpson
2023-05-18 20:04 ` [PULL v2 44/44] Hexagon (linux-user/hexagon): handle breakpoints Taylor Simpson
2023-05-19 14:55 ` [PULL v2 00/44] Hexagon update Richard Henderson
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