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From: Weiwei Li <liweiwei@iscas.ac.cn>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
	bin.meng@windriver.com, dbarboza@ventanamicro.com,
	zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn,
	lazyparser@gmail.com, Weiwei Li <liweiwei@iscas.ac.cn>
Subject: [PATCH 4/7] disas/riscv.c: Support disas for Z*inx extensions
Date: Fri, 19 May 2023 10:19:23 +0800	[thread overview]
Message-ID: <20230519021926.15362-5-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20230519021926.15362-1-liweiwei@iscas.ac.cn>

Support disas for Z*inx instructions only when Zfinx extension is supported.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 disas/riscv.c | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/disas/riscv.c b/disas/riscv.c
index 9e01810eef..a370bac6ef 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -4590,16 +4590,24 @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
             append(buf, rv_ireg_name_sym[dec->rs2], buflen);
             break;
         case '3':
-            append(buf, rv_freg_name_sym[dec->rd], buflen);
+            append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rd] :
+                                              rv_freg_name_sym[dec->rd],
+                   buflen);
             break;
         case '4':
-            append(buf, rv_freg_name_sym[dec->rs1], buflen);
+            append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs1] :
+                                              rv_freg_name_sym[dec->rs1],
+                   buflen);
             break;
         case '5':
-            append(buf, rv_freg_name_sym[dec->rs2], buflen);
+            append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs2] :
+                                              rv_freg_name_sym[dec->rs2],
+                   buflen);
             break;
         case '6':
-            append(buf, rv_freg_name_sym[dec->rs3], buflen);
+            append(buf, dec->cfg->ext_zfinx ? rv_ireg_name_sym[dec->rs3] :
+                                              rv_freg_name_sym[dec->rs3],
+                   buflen);
             break;
         case '7':
             snprintf(tmp, sizeof(tmp), "%d", dec->rs1);
-- 
2.25.1



  parent reply	other threads:[~2023-05-19  2:25 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-19  2:19 [PATCH 0/7] Add support for extension specific disas Weiwei Li
2023-05-19  2:19 ` [PATCH 1/7] disas: Change type of disassemble_info.target_info to pointer Weiwei Li
2023-05-22 12:49   ` Daniel Henrique Barboza
2023-05-19  2:19 ` [PATCH 2/7] target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info Weiwei Li
2023-05-22 12:54   ` Daniel Henrique Barboza
2023-05-22 14:20     ` Weiwei Li
2023-05-19  2:19 ` [PATCH 3/7] disas/riscv.c: Support disas for Zcm* extensions Weiwei Li
2023-05-22 13:00   ` Daniel Henrique Barboza
2023-05-22 14:24     ` Weiwei Li
2023-05-22 13:10   ` Daniel Henrique Barboza
2023-05-22 14:27     ` Weiwei Li
2023-05-22 14:30       ` Daniel Henrique Barboza
2023-05-19  2:19 ` Weiwei Li [this message]
2023-05-22 13:02   ` [PATCH 4/7] disas/riscv.c: Support disas for Z*inx extensions Daniel Henrique Barboza
2023-05-19  2:19 ` [PATCH 5/7] disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions Weiwei Li
2023-05-22 13:06   ` Daniel Henrique Barboza
2023-05-19  2:19 ` [PATCH 6/7] disas/riscv.c: Fix lines with over 80 characters Weiwei Li
2023-05-22 13:11   ` Daniel Henrique Barboza
2023-05-19  2:19 ` [PATCH 7/7] disas/riscv.c: Remove redundant parentheses Weiwei Li
2023-05-22 13:11   ` Daniel Henrique Barboza

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