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[176.184.41.228]) by smtp.gmail.com with ESMTPSA id t1-20020a7bc3c1000000b003f42158288dsm4377319wmj.20.2023.05.19.22.45.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 May 2023 22:45:34 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Liu Zhiwei , Palmer Dabbelt , Weiwei Li , Bin Meng , Alistair Francis , qemu-riscv@nongnu.org, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 4/5] hw/riscv/opentitan: Explicit machine type definition Date: Sat, 20 May 2023 07:45:09 +0200 Message-Id: <20230520054510.68822-5-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230520054510.68822-1-philmd@linaro.org> References: <20230520054510.68822-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Expand the DEFINE_MACHINE() macro, converting the class_init() handler. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/riscv/opentitan.h | 3 ++- hw/riscv/opentitan.c | 10 +++++++--- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index fd70226ed8..806ff73528 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -24,6 +24,7 @@ #include "hw/char/ibex_uart.h" #include "hw/timer/ibex_timer.h" #include "hw/ssi/ibex_spi_host.h" +#include "hw/boards.h" #include "qom/object.h" #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc" @@ -53,7 +54,7 @@ struct LowRISCIbexSoCState { MemoryRegion flash_alias; }; -#define TYPE_OPENTITAN_MACHINE "opentitan" +#define TYPE_OPENTITAN_MACHINE MACHINE_TYPE_NAME("opentitan") typedef struct OpenTitanState { /*< private >*/ diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 7d7159ea30..9535308197 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -108,8 +108,10 @@ static void opentitan_machine_init(MachineState *machine) } } -static void opentitan_machine_class_init(MachineClass *mc) +static void opentitan_machine_class_init(ObjectClass *oc, void *data) { + MachineClass *mc = MACHINE_CLASS(oc); + mc->desc = "RISC-V Board compatible with OpenTitan"; mc->init = opentitan_machine_init; mc->max_cpus = 1; @@ -118,8 +120,6 @@ static void opentitan_machine_class_init(MachineClass *mc) mc->default_ram_size = ibex_memmap[IBEX_DEV_RAM].size; } -DEFINE_MACHINE(TYPE_OPENTITAN_MACHINE, opentitan_machine_class_init) - static void lowrisc_ibex_soc_init(Object *obj) { LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj); @@ -327,6 +327,10 @@ static const TypeInfo open_titan_types[] = { .instance_size = sizeof(LowRISCIbexSoCState), .instance_init = lowrisc_ibex_soc_init, .class_init = lowrisc_ibex_soc_class_init, + }, { + .name = TYPE_OPENTITAN_MACHINE, + .parent = TYPE_MACHINE, + .class_init = opentitan_machine_class_init, } }; -- 2.38.1