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[176.184.41.228]) by smtp.gmail.com with ESMTPSA id s2-20020a7bc382000000b003f4fbd9cdb3sm1128093wmj.34.2023.05.19.22.45.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 May 2023 22:45:39 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Liu Zhiwei , Palmer Dabbelt , Weiwei Li , Bin Meng , Alistair Francis , qemu-riscv@nongnu.org, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 5/5] hw/riscv/opentitan: Correct OpenTitanState parent type/size Date: Sat, 20 May 2023 07:45:10 +0200 Message-Id: <20230520054510.68822-6-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230520054510.68822-1-philmd@linaro.org> References: <20230520054510.68822-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org OpenTitanState is the 'machine' (or 'board') state: it isn't a SysBus device, but inherits from the MachineState type. Correct the instance size. Doing so we avoid leaking an OpenTitanState pointer in opentitan_machine_init(). Fixes: fe0fe4735e ("riscv: Initial commit of OpenTitan machine") Signed-off-by: Philippe Mathieu-Daudé --- include/hw/riscv/opentitan.h | 3 ++- hw/riscv/opentitan.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index 806ff73528..609473d07b 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -55,10 +55,11 @@ struct LowRISCIbexSoCState { }; #define TYPE_OPENTITAN_MACHINE MACHINE_TYPE_NAME("opentitan") +OBJECT_DECLARE_SIMPLE_TYPE(OpenTitanState, OPENTITAN_MACHINE) typedef struct OpenTitanState { /*< private >*/ - SysBusDevice parent_obj; + MachineState parent_obj; /*< public >*/ LowRISCIbexSoCState soc; diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 9535308197..6a2fcc4ade 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -78,8 +78,8 @@ static const MemMapEntry ibex_memmap[] = { static void opentitan_machine_init(MachineState *machine) { MachineClass *mc = MACHINE_GET_CLASS(machine); + OpenTitanState *s = OPENTITAN_MACHINE(machine); const MemMapEntry *memmap = ibex_memmap; - OpenTitanState *s = g_new0(OpenTitanState, 1); MemoryRegion *sys_mem = get_system_memory(); if (machine->ram_size != mc->default_ram_size) { @@ -330,6 +330,7 @@ static const TypeInfo open_titan_types[] = { }, { .name = TYPE_OPENTITAN_MACHINE, .parent = TYPE_MACHINE, + .instance_size = sizeof(OpenTitanState), .class_init = opentitan_machine_class_init, } }; -- 2.38.1