From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org,
David Hildenbrand <david@redhat.com>,
Ilya Leoshkevich <iii@linux.ibm.com>
Subject: [PATCH 15/27] target/s390x: Use tcg_gen_qemu_{ld, st}_i128 for LPQ, STPQ
Date: Sat, 20 May 2023 09:26:22 -0700 [thread overview]
Message-ID: <20230520162634.3991009-16-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230520162634.3991009-1-richard.henderson@linaro.org>
No need to roll our own, as this is now provided by tcg.
This was the last use of retxl, so remove that too.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
Cc: qemu-s390x@nongnu.org
Cc: David Hildenbrand <david@redhat.com>
Cc: Ilya Leoshkevich <iii@linux.ibm.com>
---
target/s390x/cpu.h | 3 --
target/s390x/helper.h | 4 ---
target/s390x/tcg/mem_helper.c | 61 --------------------------------
target/s390x/tcg/translate.c | 30 +++++-----------
target/s390x/tcg/insn-data.h.inc | 2 +-
5 files changed, 9 insertions(+), 91 deletions(-)
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index c47e7adcb1..f130c29f83 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -76,9 +76,6 @@ struct CPUArchState {
float_status fpu_status; /* passed to softfloat lib */
- /* The low part of a 128-bit return, or remainder of a divide. */
- uint64_t retxl;
-
PSW psw;
S390CrashReason crash_reason;
diff --git a/target/s390x/helper.h b/target/s390x/helper.h
index 341bc51ec2..7529e725f2 100644
--- a/target/s390x/helper.h
+++ b/target/s390x/helper.h
@@ -108,10 +108,6 @@ DEF_HELPER_FLAGS_2(sfas, TCG_CALL_NO_WG, void, env, i64)
DEF_HELPER_FLAGS_2(srnm, TCG_CALL_NO_WG, void, env, i64)
DEF_HELPER_FLAGS_1(popcnt, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_2(stfle, i32, env, i64)
-DEF_HELPER_FLAGS_2(lpq, TCG_CALL_NO_WG, i64, env, i64)
-DEF_HELPER_FLAGS_2(lpq_parallel, TCG_CALL_NO_WG, i64, env, i64)
-DEF_HELPER_FLAGS_4(stpq, TCG_CALL_NO_WG, void, env, i64, i64, i64)
-DEF_HELPER_FLAGS_4(stpq_parallel, TCG_CALL_NO_WG, void, env, i64, i64, i64)
DEF_HELPER_4(mvcos, i32, env, i64, i64, i64)
DEF_HELPER_4(cu12, i32, env, i32, i32, i32)
DEF_HELPER_4(cu14, i32, env, i32, i32, i32)
diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c
index 8b58b8d88d..0e0d66b3b6 100644
--- a/target/s390x/tcg/mem_helper.c
+++ b/target/s390x/tcg/mem_helper.c
@@ -2398,67 +2398,6 @@ uint64_t HELPER(lra)(CPUS390XState *env, uint64_t addr)
}
#endif
-/* load pair from quadword */
-uint64_t HELPER(lpq)(CPUS390XState *env, uint64_t addr)
-{
- uintptr_t ra = GETPC();
- uint64_t hi, lo;
-
- check_alignment(env, addr, 16, ra);
- hi = cpu_ldq_data_ra(env, addr + 0, ra);
- lo = cpu_ldq_data_ra(env, addr + 8, ra);
-
- env->retxl = lo;
- return hi;
-}
-
-uint64_t HELPER(lpq_parallel)(CPUS390XState *env, uint64_t addr)
-{
- uintptr_t ra = GETPC();
- uint64_t hi, lo;
- int mem_idx;
- MemOpIdx oi;
- Int128 v;
-
- assert(HAVE_ATOMIC128);
-
- mem_idx = cpu_mmu_index(env, false);
- oi = make_memop_idx(MO_TEUQ | MO_ALIGN_16, mem_idx);
- v = cpu_atomic_ldo_be_mmu(env, addr, oi, ra);
- hi = int128_gethi(v);
- lo = int128_getlo(v);
-
- env->retxl = lo;
- return hi;
-}
-
-/* store pair to quadword */
-void HELPER(stpq)(CPUS390XState *env, uint64_t addr,
- uint64_t low, uint64_t high)
-{
- uintptr_t ra = GETPC();
-
- check_alignment(env, addr, 16, ra);
- cpu_stq_data_ra(env, addr + 0, high, ra);
- cpu_stq_data_ra(env, addr + 8, low, ra);
-}
-
-void HELPER(stpq_parallel)(CPUS390XState *env, uint64_t addr,
- uint64_t low, uint64_t high)
-{
- uintptr_t ra = GETPC();
- int mem_idx;
- MemOpIdx oi;
- Int128 v;
-
- assert(HAVE_ATOMIC128);
-
- mem_idx = cpu_mmu_index(env, false);
- oi = make_memop_idx(MO_TEUQ | MO_ALIGN_16, mem_idx);
- v = int128_make128(low, high);
- cpu_atomic_sto_be_mmu(env, addr, v, oi, ra);
-}
-
/* Execute instruction. This instruction executes an insn modified with
the contents of r1. It does not change the executed instruction in memory;
it does not change the program counter.
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index d6670e6a87..3eb3708d55 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -335,11 +335,6 @@ static void store_freg32_i64(int reg, TCGv_i64 v)
tcg_gen_st32_i64(v, cpu_env, freg32_offset(reg));
}
-static void return_low128(TCGv_i64 dest)
-{
- tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUS390XState, retxl));
-}
-
static void update_psw_addr(DisasContext *s)
{
/* psw.addr */
@@ -3130,15 +3125,9 @@ static DisasJumpType op_lpd(DisasContext *s, DisasOps *o)
static DisasJumpType op_lpq(DisasContext *s, DisasOps *o)
{
- if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
- gen_helper_lpq(o->out, cpu_env, o->in2);
- } else if (HAVE_ATOMIC128) {
- gen_helper_lpq_parallel(o->out, cpu_env, o->in2);
- } else {
- gen_helper_exit_atomic(cpu_env);
- return DISAS_NORETURN;
- }
- return_low128(o->out2);
+ o->out_128 = tcg_temp_new_i128();
+ tcg_gen_qemu_ld_i128(o->out_128, o->in2, get_mem_index(s),
+ MO_TE | MO_128 | MO_ALIGN);
return DISAS_NEXT;
}
@@ -4533,14 +4522,11 @@ static DisasJumpType op_stmh(DisasContext *s, DisasOps *o)
static DisasJumpType op_stpq(DisasContext *s, DisasOps *o)
{
- if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
- gen_helper_stpq(cpu_env, o->in2, o->out2, o->out);
- } else if (HAVE_ATOMIC128) {
- gen_helper_stpq_parallel(cpu_env, o->in2, o->out2, o->out);
- } else {
- gen_helper_exit_atomic(cpu_env);
- return DISAS_NORETURN;
- }
+ TCGv_i128 t16 = tcg_temp_new_i128();
+
+ tcg_gen_concat_i64_i128(t16, o->out2, o->out);
+ tcg_gen_qemu_st_i128(t16, o->in2, get_mem_index(s),
+ MO_TE | MO_128 | MO_ALIGN);
return DISAS_NEXT;
}
diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.h.inc
index 1f1ac742a9..bcc70d99ba 100644
--- a/target/s390x/tcg/insn-data.h.inc
+++ b/target/s390x/tcg/insn-data.h.inc
@@ -570,7 +570,7 @@
D(0xc804, LPD, SSF, ILA, 0, 0, new_P, r3_P32, lpd, 0, MO_TEUL)
D(0xc805, LPDG, SSF, ILA, 0, 0, new_P, r3_P64, lpd, 0, MO_TEUQ)
/* LOAD PAIR FROM QUADWORD */
- C(0xe38f, LPQ, RXY_a, Z, 0, a2, r1_P, 0, lpq, 0)
+ C(0xe38f, LPQ, RXY_a, Z, 0, a2, 0, r1_D64, lpq, 0)
/* LOAD POSITIVE */
C(0x1000, LPR, RR_a, Z, 0, r2_32s, new, r1_32, abs, abs32)
C(0xb900, LPGR, RRE, Z, 0, r2, r1, 0, abs, abs64)
--
2.34.1
next prev parent reply other threads:[~2023-05-20 16:30 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-20 16:26 [PATCH 00/27] accel/tcg: Improvements to atomic128.h Richard Henderson
2023-05-20 16:26 ` [PATCH 01/27] util: Introduce host-specific cpuinfo.h Richard Henderson
2023-05-21 10:47 ` Philippe Mathieu-Daudé
2023-05-23 15:56 ` Alex Bennée
2023-05-20 16:26 ` [PATCH 02/27] util: Add cpuinfo-i386.c Richard Henderson
2023-05-21 11:28 ` Philippe Mathieu-Daudé
2023-05-21 15:05 ` Richard Henderson
2023-05-23 16:01 ` Alex Bennée
2023-05-20 16:26 ` [PATCH 03/27] util: Add i386 CPUINFO_ATOMIC_VMOVDQU Richard Henderson
2023-05-20 16:26 ` [PATCH 04/27] tcg/i386: Use host/cpuinfo.h Richard Henderson
2023-05-20 16:26 ` [PATCH 05/27] util/bufferiszero: Use i386 host/cpuinfo.h Richard Henderson
2023-05-20 16:26 ` [PATCH 06/27] migration/xbzrle: Shuffle function order Richard Henderson
2023-05-20 16:26 ` [PATCH 07/27] migration/xbzrle: Use i386 host/cpuinfo.h Richard Henderson
2023-05-20 16:26 ` [PATCH 08/27] migration: Build migration_files once Richard Henderson
2023-05-20 16:26 ` [PATCH 09/27] util: Add cpuinfo-aarch64.c Richard Henderson
2023-05-20 16:26 ` [PATCH 10/27] include/host: Split out atomic128-cas.h Richard Henderson
2023-05-21 10:44 ` Philippe Mathieu-Daudé
2023-05-20 16:26 ` [PATCH 11/27] include/host: Split out atomic128-ldst.h Richard Henderson
2023-05-20 16:26 ` [PATCH 12/27] meson: Fix detect atomic128 support with optimization Richard Henderson
2023-05-21 10:54 ` Philippe Mathieu-Daudé
2023-05-20 16:26 ` [PATCH 13/27] include/qemu: Move CONFIG_ATOMIC128_OPT handling to atomic128.h Richard Henderson
2023-05-20 16:26 ` [PATCH 14/27] target/ppc: Use tcg_gen_qemu_{ld, st}_i128 for LQARX, LQ, STQ Richard Henderson
2023-05-20 16:26 ` Richard Henderson [this message]
2023-05-22 8:35 ` [PATCH 15/27] target/s390x: Use tcg_gen_qemu_{ld,st}_i128 for LPQ, STPQ David Hildenbrand
2023-05-22 14:15 ` Richard Henderson
2023-05-20 16:26 ` [PATCH 16/27] accel/tcg: Unify cpu_{ld,st}*_{be,le}_mmu Richard Henderson
2023-05-21 11:15 ` Philippe Mathieu-Daudé
2023-05-21 15:00 ` Richard Henderson
2023-05-22 6:39 ` Philippe Mathieu-Daudé
2023-05-22 16:24 ` Richard Henderson
2023-05-20 16:26 ` [PATCH 17/27] target/s390x: Use cpu_{ld,st}*_mmu in do_csst Richard Henderson
2023-05-21 11:21 ` Philippe Mathieu-Daudé
2023-05-21 15:01 ` Richard Henderson
2023-05-22 8:43 ` David Hildenbrand
2023-05-20 16:26 ` [PATCH 18/27] target/s390x: Always use cpu_atomic_cmpxchgl_be_mmu " Richard Henderson
2023-05-22 8:44 ` David Hildenbrand
2023-05-20 16:26 ` [PATCH 19/27] accel/tcg: Remove cpu_atomic_{ld,st}o_*_mmu Richard Henderson
2023-05-20 16:26 ` [PATCH 20/27] accel/tcg: Remove prot argument to atomic_mmu_lookup Richard Henderson
2023-05-20 16:26 ` [PATCH 21/27] accel/tcg: Eliminate #if on HAVE_ATOMIC128 and HAVE_CMPXCHG128 Richard Henderson
2023-05-20 16:26 ` [PATCH 22/27] qemu/atomic128: Split atomic16_read Richard Henderson
2023-05-20 16:26 ` [PATCH 23/27] accel/tcg: Correctly use atomic128.h in ldst_atomicity.c.inc Richard Henderson
2023-05-20 16:26 ` [PATCH 24/27] tcg: Split out tcg/debug-assert.h Richard Henderson
2023-05-21 11:25 ` Philippe Mathieu-Daudé
2023-05-20 16:26 ` [PATCH 25/27] qemu/atomic128: Improve cmpxchg fallback for atomic16_set Richard Henderson
2023-05-20 16:26 ` [PATCH 26/27] qemu/atomic128: Add runtime test for FEAT_LSE2 Richard Henderson
2023-05-20 16:26 ` [PATCH 27/27] qemu/atomic128: Add x86_64 atomic128-ldst.h Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230520162634.3991009-16-richard.henderson@linaro.org \
--to=richard.henderson@linaro.org \
--cc=david@redhat.com \
--cc=iii@linux.ibm.com \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-s390x@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).