From: Weiwei Li <liweiwei@iscas.ac.cn>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn,
lazyparser@gmail.com, Weiwei Li <liweiwei@iscas.ac.cn>
Subject: [PATCH v2 4/8] disas/riscv.c: Support disas for Zcm* extensions
Date: Tue, 23 May 2023 17:35:35 +0800 [thread overview]
Message-ID: <20230523093539.203909-5-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20230523093539.203909-1-liweiwei@iscas.ac.cn>
Support disas for Zcmt* instructions only when related extensions
are supported.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
disas/riscv.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 729ab684da..49a3eb6ac4 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -2501,7 +2501,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
op = rv_op_c_sqsp;
} else {
op = rv_op_c_fsdsp;
- if (((inst >> 12) & 0b01)) {
+ if (dec->cfg->ext_zcmp && ((inst >> 12) & 0b01)) {
switch ((inst >> 8) & 0b01111) {
case 8:
if (((inst >> 4) & 0b01111) >= 4) {
@@ -2527,6 +2527,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
} else {
switch ((inst >> 10) & 0b011) {
case 0:
+ if (!dec->cfg->ext_zcmt) {
+ break;
+ }
if (((inst >> 2) & 0xFF) >= 32) {
op = rv_op_cm_jalt;
} else {
@@ -2534,6 +2537,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
}
break;
case 3:
+ if (!dec->cfg->ext_zcmp) {
+ break;
+ }
switch ((inst >> 5) & 0b011) {
case 1: op = rv_op_cm_mvsa01; break;
case 3: op = rv_op_cm_mva01s; break;
--
2.25.1
next prev parent reply other threads:[~2023-05-23 9:37 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-23 9:35 [PATCH v2 0/8] Add support for extension specific disas Weiwei Li
2023-05-23 9:35 ` [PATCH v2 1/8] disas: Change type of disassemble_info.target_info to pointer Weiwei Li
2023-05-26 1:20 ` Alistair Francis
2023-05-23 9:35 ` [PATCH v2 2/8] target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h Weiwei Li
2023-05-23 12:15 ` Daniel Henrique Barboza
2023-05-26 1:19 ` Alistair Francis
2023-05-23 9:35 ` [PATCH v2 3/8] target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info Weiwei Li
2023-05-26 1:22 ` Alistair Francis
2023-05-23 9:35 ` Weiwei Li [this message]
2023-05-26 1:23 ` [PATCH v2 4/8] disas/riscv.c: Support disas for Zcm* extensions Alistair Francis
2023-05-23 9:35 ` [PATCH v2 5/8] disas/riscv.c: Support disas for Z*inx extensions Weiwei Li
2023-05-26 1:24 ` Alistair Francis
2023-05-23 9:35 ` [PATCH v2 6/8] disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions Weiwei Li
2023-05-26 1:25 ` Alistair Francis
2023-05-23 9:35 ` [PATCH v2 7/8] disas/riscv.c: Fix lines with over 80 characters Weiwei Li
2023-05-26 1:25 ` Alistair Francis
2023-05-23 9:35 ` [PATCH v2 8/8] disas/riscv.c: Remove redundant parentheses Weiwei Li
2023-05-26 1:26 ` Alistair Francis
2023-05-26 1:35 ` [PATCH v2 0/8] Add support for extension specific disas Alistair Francis
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