From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH v2 26/52] tcg: Add insn_start_words to TCGContext
Date: Tue, 23 May 2023 06:52:56 -0700 [thread overview]
Message-ID: <20230523135322.678948-27-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org>
This will enable replacement of TARGET_INSN_START_WORDS in tcg.c.
Split out "tcg/insn-start-words.h" and use it in target/.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/insn-start-words.h | 17 +++++++++++++++++
include/tcg/tcg-op.h | 8 ++++----
include/tcg/tcg-opc.h | 6 +++---
include/tcg/tcg.h | 9 ++-------
accel/tcg/perf.c | 8 ++++++--
accel/tcg/translate-all.c | 13 ++++++++-----
target/i386/helper.c | 2 +-
target/openrisc/sys_helper.c | 2 +-
tcg/tcg.c | 16 +++++++++++-----
9 files changed, 53 insertions(+), 28 deletions(-)
create mode 100644 include/tcg/insn-start-words.h
diff --git a/include/tcg/insn-start-words.h b/include/tcg/insn-start-words.h
new file mode 100644
index 0000000000..50c18bd326
--- /dev/null
+++ b/include/tcg/insn-start-words.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define TARGET_INSN_START_WORDS
+ * Copyright (c) 2008 Fabrice Bellard
+ */
+
+#ifndef TARGET_INSN_START_WORDS
+
+#include "cpu.h"
+
+#ifndef TARGET_INSN_START_EXTRA_WORDS
+# define TARGET_INSN_START_WORDS 1
+#else
+# define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
+#endif
+
+#endif /* TARGET_INSN_START_WORDS */
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index 47f1dce816..d63683c47b 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -22,20 +22,20 @@
# error
#endif
-#if TARGET_INSN_START_WORDS == 1
+#ifndef TARGET_INSN_START_EXTRA_WORDS
static inline void tcg_gen_insn_start(target_ulong pc)
{
TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 64 / TCG_TARGET_REG_BITS);
tcg_set_insn_start_param(op, 0, pc);
}
-#elif TARGET_INSN_START_WORDS == 2
+#elif TARGET_INSN_START_EXTRA_WORDS == 1
static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
{
TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 2 * 64 / TCG_TARGET_REG_BITS);
tcg_set_insn_start_param(op, 0, pc);
tcg_set_insn_start_param(op, 1, a1);
}
-#elif TARGET_INSN_START_WORDS == 3
+#elif TARGET_INSN_START_EXTRA_WORDS == 2
static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
target_ulong a2)
{
@@ -45,7 +45,7 @@ static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
tcg_set_insn_start_param(op, 2, a2);
}
#else
-# error "Unhandled number of operands to insn_start"
+#error Unhandled TARGET_INSN_START_EXTRA_WORDS value
#endif
#if TARGET_LONG_BITS == 32
diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
index 21594c1590..acfa5ba753 100644
--- a/include/tcg/tcg-opc.h
+++ b/include/tcg/tcg-opc.h
@@ -188,9 +188,9 @@ DEF(mulsh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulsh_i64))
#define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2)
-/* QEMU specific */
-DEF(insn_start, 0, 0, DATA64_ARGS * TARGET_INSN_START_WORDS,
- TCG_OPF_NOT_PRESENT)
+/* There are tcg_ctx->insn_start_words here, not just one. */
+DEF(insn_start, 0, 0, DATA64_ARGS, TCG_OPF_NOT_PRESENT)
+
DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END)
DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END)
DEF(goto_ptr, 0, 1, 0, TCG_OPF_BB_EXIT | TCG_OPF_BB_END)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 7c1bbba673..813c733910 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -173,12 +173,6 @@ typedef uint64_t TCGRegSet;
#define TCG_TARGET_HAS_v256 0
#endif
-#ifndef TARGET_INSN_START_EXTRA_WORDS
-# define TARGET_INSN_START_WORDS 1
-#else
-# define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
-#endif
-
typedef enum TCGOpcode {
#define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name,
#include "tcg/tcg-opc.h"
@@ -526,6 +520,7 @@ struct TCGContext {
uint8_t page_bits;
uint8_t tlb_dyn_max_bits;
#endif
+ uint8_t insn_start_words;
TCGRegSet reserved_regs;
intptr_t current_frame_offset;
@@ -597,7 +592,7 @@ struct TCGContext {
TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS];
uint16_t gen_insn_end_off[TCG_MAX_INSNS];
- uint64_t gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS];
+ uint64_t *gen_insn_data;
/* Exit to translator on overflow. */
sigjmp_buf jmp_trans;
diff --git a/accel/tcg/perf.c b/accel/tcg/perf.c
index 65e35ea3b9..f5a1eda39f 100644
--- a/accel/tcg/perf.c
+++ b/accel/tcg/perf.c
@@ -311,7 +311,8 @@ void perf_report_code(uint64_t guest_pc, TranslationBlock *tb,
const void *start)
{
struct debuginfo_query *q;
- size_t insn;
+ size_t insn, start_words;
+ uint64_t *gen_insn_data;
if (!perfmap && !jitdump) {
return;
@@ -325,9 +326,12 @@ void perf_report_code(uint64_t guest_pc, TranslationBlock *tb,
debuginfo_lock();
/* Query debuginfo for each guest instruction. */
+ gen_insn_data = tcg_ctx->gen_insn_data;
+ start_words = tcg_ctx->insn_start_words;
+
for (insn = 0; insn < tb->icount; insn++) {
/* FIXME: This replicates the restore_state_to_opc() logic. */
- q[insn].address = tcg_ctx->gen_insn_data[insn][0];
+ q[insn].address = gen_insn_data[insn * start_words + 0];
if (tb_cflags(tb) & CF_PCREL) {
q[insn].address |= (guest_pc & TARGET_PAGE_MASK);
} else {
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index be38d4aad8..03ebe58099 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -64,6 +64,7 @@
#include "tb-context.h"
#include "internal.h"
#include "perf.h"
+#include "tcg/insn-start-words.h"
/* Make sure all possible CPU event bits fit in tb->trace_vcpu_dstate */
QEMU_BUILD_BUG_ON(CPU_TRACE_DSTATE_MAX_EVENTS >
@@ -132,19 +133,20 @@ static int64_t decode_sleb128(const uint8_t **pp)
static int encode_search(TranslationBlock *tb, uint8_t *block)
{
uint8_t *highwater = tcg_ctx->code_gen_highwater;
+ uint64_t *insn_data = tcg_ctx->gen_insn_data;
uint8_t *p = block;
int i, j, n;
for (i = 0, n = tb->icount; i < n; ++i) {
uint64_t prev;
- for (j = 0; j < TARGET_INSN_START_WORDS; ++j) {
+ for (j = 0; j < TARGET_INSN_START_WORDS; ++j, ++insn_data) {
if (i == 0) {
prev = (!(tb_cflags(tb) & CF_PCREL) && j == 0 ? tb->pc : 0);
} else {
- prev = tcg_ctx->gen_insn_data[i - 1][j];
+ prev = insn_data[-TARGET_INSN_START_WORDS];
}
- p = encode_sleb128(p, tcg_ctx->gen_insn_data[i][j] - prev);
+ p = encode_sleb128(p, *insn_data - prev);
}
prev = (i == 0 ? 0 : tcg_ctx->gen_insn_end_off[i - 1]);
p = encode_sleb128(p, tcg_ctx->gen_insn_end_off[i] - prev);
@@ -364,6 +366,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
tcg_ctx->tlb_fast_offset =
(int)offsetof(ArchCPU, neg.tlb.f) - (int)offsetof(ArchCPU, env);
#endif
+ tcg_ctx->insn_start_words = TARGET_INSN_START_WORDS;
tb_overflow:
@@ -458,7 +461,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
fprintf(logfile, "OUT: [size=%d]\n", gen_code_size);
fprintf(logfile,
" -- guest addr 0x%016" PRIx64 " + tb prologue\n",
- tcg_ctx->gen_insn_data[insn][0]);
+ tcg_ctx->gen_insn_data[insn * TARGET_INSN_START_WORDS]);
chunk_start = tcg_ctx->gen_insn_end_off[insn];
disas(logfile, tb->tc.ptr, chunk_start);
@@ -471,7 +474,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
size_t chunk_end = tcg_ctx->gen_insn_end_off[insn];
if (chunk_end > chunk_start) {
fprintf(logfile, " -- guest addr 0x%016" PRIx64 "\n",
- tcg_ctx->gen_insn_data[insn][0]);
+ tcg_ctx->gen_insn_data[insn * TARGET_INSN_START_WORDS]);
disas(logfile, tb->tc.ptr + chunk_start,
chunk_end - chunk_start);
chunk_start = chunk_end;
diff --git a/target/i386/helper.c b/target/i386/helper.c
index 682d10d98a..36bf2107e7 100644
--- a/target/i386/helper.c
+++ b/target/i386/helper.c
@@ -29,7 +29,7 @@
#endif
#include "qemu/log.h"
#ifdef CONFIG_TCG
-#include "tcg/tcg.h"
+#include "tcg/insn-start-words.h"
#endif
void cpu_sync_avx_hflag(CPUX86State *env)
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 110f157601..782a5751b7 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -26,7 +26,7 @@
#ifndef CONFIG_USER_ONLY
#include "hw/boards.h"
#endif
-#include "tcg/tcg.h"
+#include "tcg/insn-start-words.h"
#define TO_SPR(group, number) (((group) << 11) + (number))
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 57600f41ac..3888a22ba1 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1506,6 +1506,8 @@ void tcg_func_start(TCGContext *s)
tcg_debug_assert(s->tlb_fast_offset < 0);
tcg_debug_assert(s->tlb_fast_offset >= MIN_TLB_MASK_TABLE_OFS);
#endif
+
+ tcg_debug_assert(s->insn_start_words > 0);
}
static TCGTemp *tcg_temp_alloc(TCGContext *s)
@@ -2450,7 +2452,7 @@ static void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs)
nb_oargs = 0;
col += ne_fprintf(f, "\n ----");
- for (i = 0; i < TARGET_INSN_START_WORDS; ++i) {
+ for (i = 0, k = s->insn_start_words; i < k; ++i) {
col += ne_fprintf(f, " %016" PRIx64,
tcg_get_insn_start_param(op, i));
}
@@ -6029,7 +6031,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start)
#ifdef CONFIG_PROFILER
TCGProfile *prof = &s->prof;
#endif
- int i, num_insns;
+ int i, start_words, num_insns;
TCGOp *op;
#ifdef CONFIG_PROFILER
@@ -6159,6 +6161,10 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start)
s->pool_labels = NULL;
#endif
+ start_words = s->insn_start_words;
+ s->gen_insn_data =
+ tcg_malloc(sizeof(uint64_t) * s->gen_tb->icount * start_words);
+
num_insns = -1;
QTAILQ_FOREACH(op, &s->ops, link) {
TCGOpcode opc = op->opc;
@@ -6184,8 +6190,8 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start)
assert(s->gen_insn_end_off[num_insns] == off);
}
num_insns++;
- for (i = 0; i < TARGET_INSN_START_WORDS; ++i) {
- s->gen_insn_data[num_insns][i] =
+ for (i = 0; i < start_words; ++i) {
+ s->gen_insn_data[num_insns * start_words + i] =
tcg_get_insn_start_param(op, i);
}
break;
@@ -6231,7 +6237,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start)
return -2;
}
}
- tcg_debug_assert(num_insns >= 0);
+ tcg_debug_assert(num_insns + 1 == s->gen_tb->icount);
s->gen_insn_end_off[num_insns] = tcg_current_code_size(s);
/* Generate TB finalization at the end of block */
--
2.34.1
next prev parent reply other threads:[~2023-05-23 13:55 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-23 13:52 [PATCH v2 00/52] tcg: Build once for system, once for user Richard Henderson
2023-05-23 13:52 ` [PATCH v2 01/52] tcg/ppc: Remove TARGET_LONG_BITS, TCG_TYPE_TL Richard Henderson
2023-05-23 13:52 ` [PATCH v2 02/52] tcg/riscv: " Richard Henderson
2023-05-23 13:52 ` [PATCH v2 03/52] tcg/s390x: " Richard Henderson
2023-05-23 13:52 ` [PATCH v2 04/52] tcg/sparc64: " Richard Henderson
2023-05-23 13:52 ` [PATCH v2 05/52] tcg: Move TCG_TYPE_TL from tcg.h to tcg-op.h Richard Henderson
2023-05-23 16:28 ` Philippe Mathieu-Daudé
2023-05-23 13:52 ` [PATCH v2 06/52] tcg: Widen CPUTLBEntry comparators to 64-bits Richard Henderson
2023-05-23 13:52 ` [PATCH v2 07/52] tcg: Add tlb_fast_offset to TCGContext Richard Henderson
2023-05-23 13:52 ` [PATCH v2 08/52] tcg: Remove TCG_TARGET_TLB_DISPLACEMENT_BITS Richard Henderson
2023-05-23 16:29 ` Philippe Mathieu-Daudé
2023-05-23 13:52 ` [PATCH v2 09/52] *: Add missing includes of qemu/error-report.h Richard Henderson
2023-05-23 13:52 ` [PATCH v2 10/52] *: Add missing includes of tcg/debug-assert.h Richard Henderson
2023-05-23 13:52 ` [PATCH v2 11/52] *: Add missing includes of tcg/tcg.h Richard Henderson
2023-05-23 16:31 ` Philippe Mathieu-Daudé
2023-05-23 13:52 ` [PATCH v2 12/52] tcg: Split out tcg-target-reg-bits.h Richard Henderson
2023-05-23 13:52 ` [PATCH v2 13/52] target/arm: Fix test of TCG_OVERSIZED_GUEST Richard Henderson
2023-05-23 13:52 ` [PATCH v2 14/52] tcg: Split out tcg/oversized-guest.h Richard Henderson
2023-05-23 16:33 ` Philippe Mathieu-Daudé
2023-05-23 13:52 ` [PATCH v2 15/52] tcg: Move TCGv, dup_const_tl definitions to tcg-op.h Richard Henderson
2023-05-23 13:52 ` [PATCH v2 16/52] tcg: Split tcg/tcg-op-common.h from tcg/tcg-op.h Richard Henderson
2023-05-23 13:52 ` [PATCH v2 17/52] target/arm: Include helper-gen.h in translator.h Richard Henderson
2023-05-23 13:52 ` [PATCH v2 18/52] target/hexagon: Include helper-gen.h where needed Richard Henderson
2023-05-23 13:52 ` [PATCH v2 19/52] tcg: Remove outdated comments in helper-head.h Richard Henderson
2023-05-23 13:52 ` [PATCH v2 20/52] tcg: Move TCGHelperInfo and dependencies to tcg/helper-info.h Richard Henderson
2023-05-23 13:52 ` [PATCH v2 21/52] tcg: Pass TCGHelperInfo to tcg_gen_callN Richard Henderson
2023-05-23 13:52 ` [PATCH v2 22/52] tcg: Move temp_idx and tcgv_i32_temp debug out of line Richard Henderson
2023-05-23 13:52 ` [PATCH v2 23/52] tcg: Split tcg_gen_callN Richard Henderson
2023-05-23 13:52 ` [PATCH v2 24/52] tcg: Split helper-gen.h Richard Henderson
2023-05-23 13:52 ` [PATCH v2 25/52] tcg: Split helper-proto.h Richard Henderson
2023-05-23 13:52 ` Richard Henderson [this message]
2023-05-23 13:52 ` [PATCH v2 27/52] tcg: Add guest_mo to TCGContext Richard Henderson
2023-05-23 13:52 ` [PATCH v2 28/52] tcg: Move TLB_FLAGS_MASK check out of get_alignment_bits Richard Henderson
2023-05-23 13:52 ` [PATCH v2 29/52] tcg: Split tcg/tcg-op-gvec.h Richard Henderson
2023-05-23 13:53 ` [PATCH v2 30/52] tcg: Remove NO_CPU_IO_DEFS Richard Henderson
2023-05-23 13:53 ` [PATCH v2 31/52] exec-all: Widen tb_page_addr_t for user-only Richard Henderson
2023-05-23 13:53 ` [PATCH v2 32/52] exec-all: Widen TranslationBlock pc and cs_base to 64-bits Richard Henderson
2023-05-23 16:36 ` Philippe Mathieu-Daudé
2023-05-23 13:53 ` [PATCH v2 33/52] tcg: Remove DEBUG_DISAS Richard Henderson
2023-05-23 16:37 ` Philippe Mathieu-Daudé
2023-05-23 13:53 ` [PATCH v2 34/52] tcg: Remove USE_TCG_OPTIMIZATIONS Richard Henderson
2023-05-23 16:37 ` Philippe Mathieu-Daudé
2023-05-23 13:53 ` [PATCH v2 35/52] tcg: Spit out exec/translation-block.h Richard Henderson
2023-05-23 13:53 ` [PATCH v2 36/52] include/exec: Remove CODE_GEN_AVG_BLOCK_SIZE Richard Henderson
2023-05-23 13:53 ` [PATCH v2 37/52] accel/tcg: Move most of gen-icount.h into translator.c Richard Henderson
2023-05-23 13:53 ` [PATCH v2 38/52] accel/tcg: Introduce translator_io_start Richard Henderson
2023-05-23 13:53 ` [PATCH v2 39/52] accel/tcg: Move translator_fake_ldb out of line Richard Henderson
2023-05-23 13:53 ` [PATCH v2 40/52] target/arm: Tidy helpers for translation Richard Henderson
2023-05-23 13:53 ` [PATCH v2 41/52] target/mips: " Richard Henderson
2023-05-23 13:53 ` [PATCH v2 42/52] *: Add missing includes of exec/translation-block.h Richard Henderson
2023-05-23 13:53 ` [PATCH v2 43/52] *: Add missing includes of exec/exec-all.h Richard Henderson
2023-05-23 13:53 ` [PATCH v2 44/52] accel/tcg: Tidy includes for translator.[ch] Richard Henderson
2023-05-23 13:53 ` [PATCH v2 45/52] tcg: Define IN_TCG Richard Henderson
2023-05-23 16:45 ` Philippe Mathieu-Daudé
2023-05-23 16:50 ` Philippe Mathieu-Daudé
2023-05-24 0:26 ` Richard Henderson
2023-05-23 13:53 ` [PATCH v2 46/52] tcg: Fix PAGE/PROT confusion Richard Henderson
2023-05-23 13:53 ` [PATCH v2 47/52] tcg: Move env defines out of NEED_CPU_H in helper-head.h Richard Henderson
2023-05-23 13:53 ` [PATCH v2 48/52] tcg: Remove target-specific headers from tcg.[ch] Richard Henderson
2023-05-23 13:53 ` [PATCH v2 49/52] plugins: Move plugin_insn_append to translator.c Richard Henderson
2023-05-23 13:53 ` [PATCH v2 50/52] plugins: Drop unused headers from exec/plugin-gen.h Richard Henderson
2023-05-23 13:53 ` [PATCH v2 51/52] exec/poison: Do not poison CONFIG_SOFTMMU Richard Henderson
2023-05-23 13:53 ` [PATCH v2 52/52] tcg: Build once for system and once for user-only Richard Henderson
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