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From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: Li Zhijian <lizhijian@cn.fujitsu.com>
Cc: <qemu-devel@nongnu.org>, <ben.widawsky@intel.com>,
	<dan.j.williams@intel.com>, <mst@redhat.com>,
	<peter.maydell@linaro.org>
Subject: Re: [PATCH 2/2] docs/clx: Change to lowercase as others
Date: Thu, 25 May 2023 12:49:30 +0100	[thread overview]
Message-ID: <20230525124930.00004ed6@Huawei.com> (raw)
In-Reply-To: <20230519085802.2106900-2-lizhijian@cn.fujitsu.com>

On Fri, 19 May 2023 16:58:02 +0800
Li Zhijian <lizhijian@cn.fujitsu.com> wrote:

> Using the same style except the 'Topo' abbreviation.
> 
> Signed-off-by: Li Zhijian <lizhijian@cn.fujitsu.com>
> ---
> I'm not a native speaker, feel free to correct me.

I've edited slightly and applied to my local staging tree for cxl patches.
Includes fixing docs/clx -> docs/cxl in the patch title.

Thanks, I'll queue this up with the next series of refactoring patches etc,

Jonathan


> ---
>  docs/system/devices/cxl.rst | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
> index d3577a4d6da..56414d25871 100644
> --- a/docs/system/devices/cxl.rst
> +++ b/docs/system/devices/cxl.rst
> @@ -157,7 +157,7 @@ responsible for allocating appropriate ranges from within the CFMWs
>  and exposing those via normal memory configurations as would be done
>  for system RAM.
>  
> -Example system Topology. x marks the match in each decoder level::
> +Example system topology. x marks the match in each decoder level::
>  
>    |<------------------SYSTEM PHYSICAL ADDRESS MAP (1)----------------->|
>    |    __________   __________________________________   __________    |
> @@ -187,8 +187,8 @@ Example system Topology. x marks the match in each decoder level::
>         ___________|___   __________|__   __|_________   ___|_________
>     (3)|  Root Port 0  | | Root Port 1 | | Root Port 2| | Root Port 3 |
>        |  Appears in   | | Appears in  | | Appears in | | Appear in   |
> -      |  PCI topology | | PCI Topology| | PCI Topo   | | PCI Topo    |
> -      |  As 0c:00.0   | | as 0c:01.0  | | as de:00.0 | | as de:01.0  |
> +      |  PCI topology | | PCI topology| | PCI Topo   | | PCI Topo    |

I've switched to topo for the abbreviation as well.  No particular reason
it should have a capital letter.

> +      |  as 0c:00.0   | | as 0c:01.0  | | as de:00.0 | | as de:01.0  |
>        |_______________| |_____________| |____________| |_____________|
>              |                  |               |              |
>              |                  |               |              |
> @@ -272,7 +272,7 @@ Example topology involving a switch::
>        |  Root Port 0  |
>        |  Appears in   |
>        |  PCI topology |
> -      |  As 0c:00.0   |
> +      |  as 0c:00.0   |
>        |___________x___|
>                    |
>                    |



  reply	other threads:[~2023-05-25 11:50 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-19  8:58 [PATCH 1/2] docs/cxl: Correct CFMW number Li Zhijian
2023-05-19  8:58 ` [PATCH 2/2] docs/clx: Change to lowercase as others Li Zhijian
2023-05-25 11:49   ` Jonathan Cameron via [this message]
2023-05-26  2:37     ` Zhijian Li (Fujitsu)
2023-05-25 11:42 ` [PATCH 1/2] docs/cxl: Correct CFMW number Jonathan Cameron via

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