* [PATCH 1/2] docs/cxl: Correct CFMW number
@ 2023-05-19 8:58 Li Zhijian
2023-05-19 8:58 ` [PATCH 2/2] docs/clx: Change to lowercase as others Li Zhijian
2023-05-25 11:42 ` [PATCH 1/2] docs/cxl: Correct CFMW number Jonathan Cameron via
0 siblings, 2 replies; 5+ messages in thread
From: Li Zhijian @ 2023-05-19 8:58 UTC (permalink / raw)
To: Jonathan.Cameron, qemu-devel
Cc: ben.widawsky, dan.j.williams, mst, peter.maydell, Li Zhijian
The 'Notes:' in this document mentioned CFMW{0-2}, but the figure missed
CFMW2.
Signed-off-by: Li Zhijian <lizhijian@cn.fujitsu.com>
---
I'm totally new to CXL, so i have little confidence to this change :)
---
docs/system/devices/cxl.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
index dce43476129..d3577a4d6da 100644
--- a/docs/system/devices/cxl.rst
+++ b/docs/system/devices/cxl.rst
@@ -162,7 +162,7 @@ Example system Topology. x marks the match in each decoder level::
|<------------------SYSTEM PHYSICAL ADDRESS MAP (1)----------------->|
| __________ __________________________________ __________ |
| | | | | | | |
- | | CFMW 0 | | CXL Fixed Memory Window 1 | | CFMW 1 | |
+ | | CFMW 0 | | CXL Fixed Memory Window 1 | | CFMW 2 | |
| | HB0 only | | Configured to interleave memory | | HB1 only | |
| | | | memory accesses across HB0/HB1 | | | |
| |__________| |_____x____________________________| |__________| |
@@ -247,7 +247,7 @@ Example topology involving a switch::
|<------------------SYSTEM PHYSICAL ADDRESS MAP (1)----------------->|
| __________ __________________________________ __________ |
| | | | | | | |
- | | CFMW 0 | | CXL Fixed Memory Window 1 | | CFMW 1 | |
+ | | CFMW 0 | | CXL Fixed Memory Window 1 | | CFMW 2 | |
| | HB0 only | | Configured to interleave memory | | HB1 only | |
| | | | memory accesses across HB0/HB1 | | | |
| |____x_____| |__________________________________| |__________| |
--
2.31.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH 2/2] docs/clx: Change to lowercase as others
2023-05-19 8:58 [PATCH 1/2] docs/cxl: Correct CFMW number Li Zhijian
@ 2023-05-19 8:58 ` Li Zhijian
2023-05-25 11:49 ` Jonathan Cameron via
2023-05-25 11:42 ` [PATCH 1/2] docs/cxl: Correct CFMW number Jonathan Cameron via
1 sibling, 1 reply; 5+ messages in thread
From: Li Zhijian @ 2023-05-19 8:58 UTC (permalink / raw)
To: Jonathan.Cameron, qemu-devel
Cc: ben.widawsky, dan.j.williams, mst, peter.maydell, Li Zhijian
Using the same style except the 'Topo' abbreviation.
Signed-off-by: Li Zhijian <lizhijian@cn.fujitsu.com>
---
I'm not a native speaker, feel free to correct me.
---
docs/system/devices/cxl.rst | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
index d3577a4d6da..56414d25871 100644
--- a/docs/system/devices/cxl.rst
+++ b/docs/system/devices/cxl.rst
@@ -157,7 +157,7 @@ responsible for allocating appropriate ranges from within the CFMWs
and exposing those via normal memory configurations as would be done
for system RAM.
-Example system Topology. x marks the match in each decoder level::
+Example system topology. x marks the match in each decoder level::
|<------------------SYSTEM PHYSICAL ADDRESS MAP (1)----------------->|
| __________ __________________________________ __________ |
@@ -187,8 +187,8 @@ Example system Topology. x marks the match in each decoder level::
___________|___ __________|__ __|_________ ___|_________
(3)| Root Port 0 | | Root Port 1 | | Root Port 2| | Root Port 3 |
| Appears in | | Appears in | | Appears in | | Appear in |
- | PCI topology | | PCI Topology| | PCI Topo | | PCI Topo |
- | As 0c:00.0 | | as 0c:01.0 | | as de:00.0 | | as de:01.0 |
+ | PCI topology | | PCI topology| | PCI Topo | | PCI Topo |
+ | as 0c:00.0 | | as 0c:01.0 | | as de:00.0 | | as de:01.0 |
|_______________| |_____________| |____________| |_____________|
| | | |
| | | |
@@ -272,7 +272,7 @@ Example topology involving a switch::
| Root Port 0 |
| Appears in |
| PCI topology |
- | As 0c:00.0 |
+ | as 0c:00.0 |
|___________x___|
|
|
--
2.31.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH 2/2] docs/clx: Change to lowercase as others
2023-05-19 8:58 ` [PATCH 2/2] docs/clx: Change to lowercase as others Li Zhijian
@ 2023-05-25 11:49 ` Jonathan Cameron via
2023-05-26 2:37 ` Zhijian Li (Fujitsu)
0 siblings, 1 reply; 5+ messages in thread
From: Jonathan Cameron via @ 2023-05-25 11:49 UTC (permalink / raw)
To: Li Zhijian; +Cc: qemu-devel, ben.widawsky, dan.j.williams, mst, peter.maydell
On Fri, 19 May 2023 16:58:02 +0800
Li Zhijian <lizhijian@cn.fujitsu.com> wrote:
> Using the same style except the 'Topo' abbreviation.
>
> Signed-off-by: Li Zhijian <lizhijian@cn.fujitsu.com>
> ---
> I'm not a native speaker, feel free to correct me.
I've edited slightly and applied to my local staging tree for cxl patches.
Includes fixing docs/clx -> docs/cxl in the patch title.
Thanks, I'll queue this up with the next series of refactoring patches etc,
Jonathan
> ---
> docs/system/devices/cxl.rst | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
> index d3577a4d6da..56414d25871 100644
> --- a/docs/system/devices/cxl.rst
> +++ b/docs/system/devices/cxl.rst
> @@ -157,7 +157,7 @@ responsible for allocating appropriate ranges from within the CFMWs
> and exposing those via normal memory configurations as would be done
> for system RAM.
>
> -Example system Topology. x marks the match in each decoder level::
> +Example system topology. x marks the match in each decoder level::
>
> |<------------------SYSTEM PHYSICAL ADDRESS MAP (1)----------------->|
> | __________ __________________________________ __________ |
> @@ -187,8 +187,8 @@ Example system Topology. x marks the match in each decoder level::
> ___________|___ __________|__ __|_________ ___|_________
> (3)| Root Port 0 | | Root Port 1 | | Root Port 2| | Root Port 3 |
> | Appears in | | Appears in | | Appears in | | Appear in |
> - | PCI topology | | PCI Topology| | PCI Topo | | PCI Topo |
> - | As 0c:00.0 | | as 0c:01.0 | | as de:00.0 | | as de:01.0 |
> + | PCI topology | | PCI topology| | PCI Topo | | PCI Topo |
I've switched to topo for the abbreviation as well. No particular reason
it should have a capital letter.
> + | as 0c:00.0 | | as 0c:01.0 | | as de:00.0 | | as de:01.0 |
> |_______________| |_____________| |____________| |_____________|
> | | | |
> | | | |
> @@ -272,7 +272,7 @@ Example topology involving a switch::
> | Root Port 0 |
> | Appears in |
> | PCI topology |
> - | As 0c:00.0 |
> + | as 0c:00.0 |
> |___________x___|
> |
> |
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] docs/clx: Change to lowercase as others
2023-05-25 11:49 ` Jonathan Cameron via
@ 2023-05-26 2:37 ` Zhijian Li (Fujitsu)
0 siblings, 0 replies; 5+ messages in thread
From: Zhijian Li (Fujitsu) @ 2023-05-26 2:37 UTC (permalink / raw)
To: Jonathan Cameron, Zhijian Li (Fujitsu)
Cc: qemu-devel@nongnu.org, ben.widawsky@intel.com,
dan.j.williams@intel.com, mst@redhat.com,
peter.maydell@linaro.org
On 25/05/2023 19:49, Jonathan Cameron via wrote:
> On Fri, 19 May 2023 16:58:02 +0800
> Li Zhijian <lizhijian@cn.fujitsu.com> wrote:
>
>> Using the same style except the 'Topo' abbreviation.
>>
>> Signed-off-by: Li Zhijian <lizhijian@cn.fujitsu.com>
>> ---
>> I'm not a native speaker, feel free to correct me.
>
> I've edited slightly and applied to my local staging tree for cxl patches.
> Includes fixing docs/clx -> docs/cxl in the patch title.
> Thanks, I'll queue this up with the next series of refactoring patches etc,
Thank you for your help.
Thanks
Zhijian
>
> Jonathan
>
>
>> ---
>> docs/system/devices/cxl.rst | 8 ++++----
>> 1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
>> index d3577a4d6da..56414d25871 100644
>> --- a/docs/system/devices/cxl.rst
>> +++ b/docs/system/devices/cxl.rst
>> @@ -157,7 +157,7 @@ responsible for allocating appropriate ranges from within the CFMWs
>> and exposing those via normal memory configurations as would be done
>> for system RAM.
>>
>> -Example system Topology. x marks the match in each decoder level::
>> +Example system topology. x marks the match in each decoder level::
>>
>> |<------------------SYSTEM PHYSICAL ADDRESS MAP (1)----------------->|
>> | __________ __________________________________ __________ |
>> @@ -187,8 +187,8 @@ Example system Topology. x marks the match in each decoder level::
>> ___________|___ __________|__ __|_________ ___|_________
>> (3)| Root Port 0 | | Root Port 1 | | Root Port 2| | Root Port 3 |
>> | Appears in | | Appears in | | Appears in | | Appear in |
>> - | PCI topology | | PCI Topology| | PCI Topo | | PCI Topo |
>> - | As 0c:00.0 | | as 0c:01.0 | | as de:00.0 | | as de:01.0 |
>> + | PCI topology | | PCI topology| | PCI Topo | | PCI Topo |
>
> I've switched to topo for the abbreviation as well. No particular reason
> it should have a capital letter.
>
>> + | as 0c:00.0 | | as 0c:01.0 | | as de:00.0 | | as de:01.0 |
>> |_______________| |_____________| |____________| |_____________|
>> | | | |
>> | | | |
>> @@ -272,7 +272,7 @@ Example topology involving a switch::
>> | Root Port 0 |
>> | Appears in |
>> | PCI topology |
>> - | As 0c:00.0 |
>> + | as 0c:00.0 |
>> |___________x___|
>> |
>> |
>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] docs/cxl: Correct CFMW number
2023-05-19 8:58 [PATCH 1/2] docs/cxl: Correct CFMW number Li Zhijian
2023-05-19 8:58 ` [PATCH 2/2] docs/clx: Change to lowercase as others Li Zhijian
@ 2023-05-25 11:42 ` Jonathan Cameron via
1 sibling, 0 replies; 5+ messages in thread
From: Jonathan Cameron via @ 2023-05-25 11:42 UTC (permalink / raw)
To: Li Zhijian; +Cc: qemu-devel, ben.widawsky, dan.j.williams, mst, peter.maydell
On Fri, 19 May 2023 16:58:01 +0800
Li Zhijian <lizhijian@cn.fujitsu.com> wrote:
> The 'Notes:' in this document mentioned CFMW{0-2}, but the figure missed
> CFMW2.
>
> Signed-off-by: Li Zhijian <lizhijian@cn.fujitsu.com>
> ---
> I'm totally new to CXL, so i have little confidence to this change :)
I believe this one is already fixed upstream by Brice Goglin
https://gitlab.com/qemu-project/qemu/-/commit/ca4750583a597e97cbf8cec008d228f95d22c4
Otherwise was good!
Thanks,
Jonathan
> ---
> docs/system/devices/cxl.rst | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst
> index dce43476129..d3577a4d6da 100644
> --- a/docs/system/devices/cxl.rst
> +++ b/docs/system/devices/cxl.rst
> @@ -162,7 +162,7 @@ Example system Topology. x marks the match in each decoder level::
> |<------------------SYSTEM PHYSICAL ADDRESS MAP (1)----------------->|
> | __________ __________________________________ __________ |
> | | | | | | | |
> - | | CFMW 0 | | CXL Fixed Memory Window 1 | | CFMW 1 | |
> + | | CFMW 0 | | CXL Fixed Memory Window 1 | | CFMW 2 | |
> | | HB0 only | | Configured to interleave memory | | HB1 only | |
> | | | | memory accesses across HB0/HB1 | | | |
> | |__________| |_____x____________________________| |__________| |
> @@ -247,7 +247,7 @@ Example topology involving a switch::
> |<------------------SYSTEM PHYSICAL ADDRESS MAP (1)----------------->|
> | __________ __________________________________ __________ |
> | | | | | | | |
> - | | CFMW 0 | | CXL Fixed Memory Window 1 | | CFMW 1 | |
> + | | CFMW 0 | | CXL Fixed Memory Window 1 | | CFMW 2 | |
> | | HB0 only | | Configured to interleave memory | | HB1 only | |
> | | | | memory accesses across HB0/HB1 | | | |
> | |____x_____| |__________________________________| |__________| |
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-05-26 2:38 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-05-19 8:58 [PATCH 1/2] docs/cxl: Correct CFMW number Li Zhijian
2023-05-19 8:58 ` [PATCH 2/2] docs/clx: Change to lowercase as others Li Zhijian
2023-05-25 11:49 ` Jonathan Cameron via
2023-05-26 2:37 ` Zhijian Li (Fujitsu)
2023-05-25 11:42 ` [PATCH 1/2] docs/cxl: Correct CFMW number Jonathan Cameron via
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).