From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Alistair Francis <alistair.francis@wdc.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PULL 19/23] tcg/riscv: Support REV8 from Zbb
Date: Thu, 25 May 2023 11:10:32 -0700 [thread overview]
Message-ID: <20230525181036.1559435-20-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230525181036.1559435-1-richard.henderson@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/riscv/tcg-target.h | 10 +++++-----
tcg/riscv/tcg-target.c.inc | 29 +++++++++++++++++++++++++++++
2 files changed, 34 insertions(+), 5 deletions(-)
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index 317d385924..8e327afc3a 100644
--- a/tcg/riscv/tcg-target.h
+++ b/tcg/riscv/tcg-target.h
@@ -116,8 +116,8 @@ extern bool have_zbb;
#define TCG_TARGET_HAS_ext16s_i32 1
#define TCG_TARGET_HAS_ext8u_i32 1
#define TCG_TARGET_HAS_ext16u_i32 1
-#define TCG_TARGET_HAS_bswap16_i32 0
-#define TCG_TARGET_HAS_bswap32_i32 0
+#define TCG_TARGET_HAS_bswap16_i32 have_zbb
+#define TCG_TARGET_HAS_bswap32_i32 have_zbb
#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_neg_i32 1
#define TCG_TARGET_HAS_andc_i32 have_zbb
@@ -149,9 +149,9 @@ extern bool have_zbb;
#define TCG_TARGET_HAS_ext8u_i64 1
#define TCG_TARGET_HAS_ext16u_i64 1
#define TCG_TARGET_HAS_ext32u_i64 1
-#define TCG_TARGET_HAS_bswap16_i64 0
-#define TCG_TARGET_HAS_bswap32_i64 0
-#define TCG_TARGET_HAS_bswap64_i64 0
+#define TCG_TARGET_HAS_bswap16_i64 have_zbb
+#define TCG_TARGET_HAS_bswap32_i64 have_zbb
+#define TCG_TARGET_HAS_bswap64_i64 have_zbb
#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_neg_i64 1
#define TCG_TARGET_HAS_andc_i64 have_zbb
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index cc96425413..cb4afb4733 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -1487,6 +1487,30 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
+ case INDEX_op_bswap64_i64:
+ tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0);
+ break;
+ case INDEX_op_bswap32_i32:
+ a2 = 0;
+ /* fall through */
+ case INDEX_op_bswap32_i64:
+ tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0);
+ if (a2 & TCG_BSWAP_OZ) {
+ tcg_out_opc_imm(s, OPC_SRLI, a0, a0, 32);
+ } else {
+ tcg_out_opc_imm(s, OPC_SRAI, a0, a0, 32);
+ }
+ break;
+ case INDEX_op_bswap16_i64:
+ case INDEX_op_bswap16_i32:
+ tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0);
+ if (a2 & TCG_BSWAP_OZ) {
+ tcg_out_opc_imm(s, OPC_SRLI, a0, a0, 48);
+ } else {
+ tcg_out_opc_imm(s, OPC_SRAI, a0, a0, 48);
+ }
+ break;
+
case INDEX_op_add2_i32:
tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
const_args[4], const_args[5], false, true);
@@ -1608,6 +1632,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_extrl_i64_i32:
case INDEX_op_extrh_i64_i32:
case INDEX_op_ext_i32_i64:
+ case INDEX_op_bswap16_i32:
+ case INDEX_op_bswap32_i32:
+ case INDEX_op_bswap16_i64:
+ case INDEX_op_bswap32_i64:
+ case INDEX_op_bswap64_i64:
return C_O1_I1(r, r);
case INDEX_op_st8_i32:
--
2.34.1
next prev parent reply other threads:[~2023-05-25 18:15 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-25 18:10 [PULL 00/23] tcg patch queue Richard Henderson
2023-05-25 18:10 ` [PULL 01/23] tcg/mips: Move TCG_AREG0 to S8 Richard Henderson
2023-05-25 18:10 ` [PULL 02/23] tcg/mips: Move TCG_GUEST_BASE_REG to S7 Richard Henderson
2023-05-25 18:10 ` [PULL 03/23] tcg/mips: Unify TCG_GUEST_BASE_REG tests Richard Henderson
2023-05-25 18:10 ` [PULL 04/23] tcg/mips: Create and use TCG_REG_TB Richard Henderson
2023-05-25 18:10 ` [PULL 05/23] tcg/mips: Split out tcg_out_movi_one Richard Henderson
2023-05-25 18:10 ` [PULL 06/23] tcg/mips: Split out tcg_out_movi_two Richard Henderson
2023-05-25 18:10 ` [PULL 07/23] tcg/mips: Use the constant pool for 64-bit constants Richard Henderson
2023-05-25 18:10 ` [PULL 08/23] tcg/mips: Aggressively use the constant pool for n64 calls Richard Henderson
2023-05-25 18:10 ` [PULL 09/23] tcg/mips: Try tb-relative addresses in tcg_out_movi Richard Henderson
2023-05-25 18:10 ` [PULL 10/23] tcg/mips: Try three insns with shift and add " Richard Henderson
2023-05-25 18:10 ` [PULL 11/23] tcg/mips: Use qemu_build_not_reached for LO/HI_OFF Richard Henderson
2023-05-25 18:10 ` [PULL 12/23] tcg/mips: Replace MIPS_BE with HOST_BIG_ENDIAN Richard Henderson
2023-05-25 18:10 ` [PULL 13/23] disas/riscv: Decode czero.{eqz,nez} Richard Henderson
2023-05-25 18:10 ` [PULL 14/23] tcg/riscv: Probe for Zba, Zbb, Zicond extensions Richard Henderson
2023-05-25 18:10 ` [PULL 15/23] tcg/riscv: Support ANDN, ORN, XNOR from Zbb Richard Henderson
2023-05-25 18:10 ` [PULL 16/23] tcg/riscv: Support ADD.UW, SEXT.B, SEXT.H, ZEXT.H from Zba+Zbb Richard Henderson
2023-05-25 18:10 ` [PULL 17/23] tcg/riscv: Use ADD.UW for guest address generation Richard Henderson
2023-05-25 18:10 ` [PULL 18/23] tcg/riscv: Support rotates from Zbb Richard Henderson
2023-05-25 18:10 ` Richard Henderson [this message]
2023-05-25 18:10 ` [PULL 20/23] tcg/riscv: Support CPOP " Richard Henderson
2023-05-25 18:10 ` [PULL 21/23] tcg/riscv: Improve setcond expansion Richard Henderson
2023-05-25 18:10 ` [PULL 22/23] tcg/riscv: Implement movcond Richard Henderson
2023-05-25 18:10 ` [PULL 23/23] tcg/riscv: Support CTZ, CLZ from Zbb Richard Henderson
2023-05-25 19:32 ` [PULL 00/23] tcg patch queue Richard Henderson
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