From: Weiwei Li <liweiwei@iscas.ac.cn>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com,
bin.meng@windriver.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, wangjunqiang@iscas.ac.cn,
lazyparser@gmail.com, Weiwei Li <liweiwei@iscas.ac.cn>,
Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v3 7/7] target/riscv: Remove pc_succ_insn from DisasContext
Date: Fri, 26 May 2023 15:21:24 +0800 [thread overview]
Message-ID: <20230526072124.298466-8-liweiwei@iscas.ac.cn> (raw)
In-Reply-To: <20230526072124.298466-1-liweiwei@iscas.ac.cn>
pc_succ_insn is no longer useful after the introduce of cur_insn_len
and all pc related value use diff value instead of absolute value.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 87031015d3..859d5b2dcf 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -57,8 +57,6 @@ typedef enum {
typedef struct DisasContext {
DisasContextBase base;
- /* pc_succ_insn points to the instruction following base.pc_next */
- target_ulong pc_succ_insn;
target_ulong cur_insn_len;
target_ulong pc_save;
target_ulong priv_ver;
@@ -1147,7 +1145,6 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
/* Check for compressed insn */
if (ctx->cur_insn_len == 2) {
ctx->opcode = opcode;
- ctx->pc_succ_insn = ctx->base.pc_next + 2;
/*
* The Zca extension is added as way to refer to instructions in the C
* extension that do not include the floating-point loads and stores
@@ -1162,7 +1159,6 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
translator_lduw(env, &ctx->base,
ctx->base.pc_next + 2));
ctx->opcode = opcode32;
- ctx->pc_succ_insn = ctx->base.pc_next + 4;
for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
if (decoders[i].guard_func(ctx) &&
@@ -1183,7 +1179,6 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
uint32_t tb_flags = ctx->base.tb->flags;
ctx->pc_save = ctx->base.pc_first;
- ctx->pc_succ_insn = ctx->base.pc_first;
ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV);
ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS);
@@ -1236,7 +1231,7 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
ctx->ol = ctx->xl;
decode_opc(env, ctx, opcode16);
- ctx->base.pc_next = ctx->pc_succ_insn;
+ ctx->base.pc_next += ctx->cur_insn_len;
/* Only the first insn within a TB is allowed to cross a page boundary. */
if (ctx->base.is_jmp == DISAS_NEXT) {
--
2.25.1
next prev parent reply other threads:[~2023-05-26 7:22 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-26 7:21 [PATCH v3 0/7] target/riscv: Add support for PC-relative translation Weiwei Li
2023-05-26 7:21 ` [PATCH v3 1/7] target/riscv: Fix target address to update badaddr Weiwei Li
2023-05-26 7:21 ` [PATCH v3 2/7] target/riscv: Introduce cur_insn_len into DisasContext Weiwei Li
2023-05-26 7:21 ` [PATCH v3 3/7] target/riscv: Change gen_goto_tb to work on displacements Weiwei Li
2023-05-26 7:21 ` [PATCH v3 4/7] target/riscv: Change gen_set_pc_imm to gen_update_pc Weiwei Li
2023-05-26 7:21 ` [PATCH v3 5/7] target/riscv: Use true diff for gen_pc_plus_diff Weiwei Li
2023-05-26 7:21 ` [PATCH v3 6/7] target/riscv: Enable PC-relative translation Weiwei Li
2023-05-26 7:21 ` Weiwei Li [this message]
2023-06-01 5:20 ` [PATCH v3 0/7] target/riscv: Add support for " Alistair Francis
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