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[200.162.225.121]) by smtp.gmail.com with ESMTPSA id w4-20020a4adec4000000b0054f85f67f31sm3378830oou.46.2023.05.28.09.49.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 May 2023 09:49:42 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, danielhb413@gmail.com, peter.maydell@linaro.org, richard.henderson@linaro.org, Nicholas Piggin , Fabiano Rosas Subject: [PULL 03/10] target/ppc: Alignment faults do not set DSISR in ISA v3.0 onward Date: Sun, 28 May 2023 13:49:15 -0300 Message-Id: <20230528164922.20364-4-danielhb413@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230528164922.20364-1-danielhb413@gmail.com> References: <20230528164922.20364-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::233; envelope-from=danielhb413@gmail.com; helo=mail-oi1-x233.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Nicholas Piggin This optional behavior was removed from the ISA in v3.0, see Summary of Changes preface: Data Storage Interrupt Status Register for Alignment Interrupt: Simplifies the Alignment interrupt by remov- ing the Data Storage Interrupt Status Register (DSISR) from the set of registers modified by the Alignment interrupt. Reviewed-by: Fabiano Rosas Signed-off-by: Nicholas Piggin Message-Id: <20230515092655.171206-5-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza --- target/ppc/excp_helper.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 199328f4b6..fea9221501 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1431,13 +1431,16 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp) break; } case POWERPC_EXCP_ALIGN: /* Alignment exception */ - /* Get rS/rD and rA from faulting opcode */ - /* - * Note: the opcode fields will not be set properly for a - * direct store load/store, but nobody cares as nobody - * actually uses direct store segments. - */ - env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; + /* Optional DSISR update was removed from ISA v3.0 */ + if (!(env->insns_flags2 & PPC2_ISA300)) { + /* Get rS/rD and rA from faulting opcode */ + /* + * Note: the opcode fields will not be set properly for a + * direct store load/store, but nobody cares as nobody + * actually uses direct store segments. + */ + env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16; + } break; case POWERPC_EXCP_PROGRAM: /* Program exception */ switch (env->error_code & ~0xF) { -- 2.40.1