From: Zhao Liu <zhao1.liu@linux.intel.com>
To: "Eduardo Habkost" <eduardo@habkost.net>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Yanan Wang" <wangyanan55@huawei.com>,
"Michael S . Tsirkin" <mst@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>
Cc: qemu-devel@nongnu.org, Zhenyu Wang <zhenyu.z.wang@intel.com>,
Xiaoyao Li <xiaoyao.li@intel.com>,
Babu Moger <babu.moger@amd.com>, Zhao Liu <zhao1.liu@intel.com>,
Zhuocheng Ding <zhuocheng.ding@intel.com>
Subject: [PATCH v2 07/17] i386: Introduce module-level cpu topology to CPUX86State
Date: Mon, 29 May 2023 20:30:51 +0800 [thread overview]
Message-ID: <20230529123101.411267-8-zhao1.liu@linux.intel.com> (raw)
In-Reply-To: <20230529123101.411267-1-zhao1.liu@linux.intel.com>
From: Zhuocheng Ding <zhuocheng.ding@intel.com>
smp command has the "clusters" parameter but x86 hasn't supported that
level. "cluster" is a CPU topology level concept above cores, in which
the cores may share some resources (L2 cache or some others like L3
cache tags, depending on the Archs) [1][2]. For x86, the resource shared
by cores at the cluster level is mainly the L2 cache.
However, using cluster to define x86's L2 cache topology will cause the
compatibility problem:
Currently, x86 defaults that the L2 cache is shared in one core, which
actually implies a default setting "cores per L2 cache is 1" and
therefore implicitly defaults to having as many L2 caches as cores.
For example (i386 PC machine):
-smp 16,sockets=2,dies=2,cores=2,threads=2,maxcpus=16 (*)
Considering the topology of the L2 cache, this (*) implicitly means "1
core per L2 cache" and "2 L2 caches per die".
If we use cluster to configure L2 cache topology with the new default
setting "clusters per L2 cache is 1", the above semantics will change
to "2 cores per cluster" and "1 cluster per L2 cache", that is, "2
cores per L2 cache".
So the same command (*) will cause changes in the L2 cache topology,
further affecting the performance of the virtual machine.
Therefore, x86 should only treat cluster as a cpu topology level and
avoid using it to change L2 cache by default for compatibility.
"cluster" in smp is the CPU topology level which is between "core" and
die.
For x86, the "cluster" in smp is corresponding to the module level [2],
which is above the core level. So use the "module" other than "cluster"
in i386 code.
And please note that x86 already has a cpu topology level also named
"cluster" [3], this level is at the upper level of the package. Here,
the cluster in x86 cpu topology is completely different from the
"clusters" as the smp parameter. After the module level is introduced,
the cluster as the smp parameter will actually refer to the module level
of x86.
[1]: 864c3b5c32f0 ("hw/core/machine: Introduce CPU cluster topology support")
[2]: Yanan's comment about "cluster",
https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg04051.html
[3]: SDM, vol.3, ch.9, 9.9.1 Hierarchical Mapping of Shared Resources.
Signed-off-by: Zhuocheng Ding <zhuocheng.ding@intel.com>
Co-developed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
Changes since v1:
* The background of the introduction of the "cluster" parameter and its
exact meaning were revised according to Yanan's explanation. (Yanan)
---
hw/i386/x86.c | 1 +
target/i386/cpu.c | 1 +
target/i386/cpu.h | 5 +++++
3 files changed, 7 insertions(+)
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index a88a126123be..4efc390905ff 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -309,6 +309,7 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev,
init_topo_info(&topo_info, x86ms);
env->nr_dies = ms->smp.dies;
+ env->nr_modules = ms->smp.clusters;
/*
* If APIC ID is not set,
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index b069b43ff999..05a5afd42a81 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -7332,6 +7332,7 @@ static void x86_cpu_initfn(Object *obj)
CPUX86State *env = &cpu->env;
env->nr_dies = 1;
+ env->nr_modules = 1;
cpu_set_cpustate_pointers(cpu);
object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 724ffd2b1fc9..fb8f7cb24902 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1872,6 +1872,11 @@ typedef struct CPUArchState {
/* Number of dies within this CPU package. */
unsigned nr_dies;
+ /*
+ * Number of modules within this CPU package.
+ * Module level in x86 cpu topology is corresponding to smp.clusters.
+ */
+ unsigned nr_modules;
} CPUX86State;
struct kvm_msrs;
--
2.34.1
next prev parent reply other threads:[~2023-05-29 12:23 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-29 12:30 [PATCH v2 00/17] Support smp.clusters for x86 Zhao Liu
2023-05-29 12:30 ` [PATCH v2 01/17] i386: Fix comment style in topology.h Zhao Liu
2023-05-29 12:30 ` [PATCH v2 02/17] tests: Rename test-x86-cpuid.c to test-x86-topo.c Zhao Liu
2023-06-28 6:21 ` Philippe Mathieu-Daudé
2023-05-29 12:30 ` [PATCH v2 03/17] softmmu: Fix CPUSTATE.nr_cores' calculation Zhao Liu
2023-05-29 12:30 ` [PATCH v2 04/17] i386/cpu: Fix i/d-cache topology to core level for Intel CPU Zhao Liu
2023-05-29 12:30 ` [PATCH v2 05/17] i386/cpu: Use APIC ID offset to encode cache topo in CPUID[4] Zhao Liu
2023-05-29 12:30 ` [PATCH v2 06/17] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid() Zhao Liu
2023-05-29 12:30 ` Zhao Liu [this message]
2023-05-29 12:30 ` [PATCH v2 08/17] i386: Support modules_per_die in X86CPUTopoInfo Zhao Liu
2023-05-29 12:30 ` [PATCH v2 09/17] i386: Support module_id in X86CPUTopoIDs Zhao Liu
2023-05-29 12:30 ` [PATCH v2 10/17] i386/cpu: Introduce cluster-id to X86CPU Zhao Liu
2023-05-29 12:30 ` [PATCH v2 11/17] tests: Add test case of APIC ID for module level parsing Zhao Liu
2023-05-29 12:30 ` [PATCH v2 12/17] hw/i386/pc: Support smp.clusters for x86 PC machine Zhao Liu
2023-05-29 12:30 ` [PATCH v2 13/17] i386: Add cache topology info in CPUCacheInfo Zhao Liu
2023-05-29 12:30 ` [PATCH v2 14/17] i386: Use CPUCacheInfo.share_level to encode CPUID[4] Zhao Liu
2023-05-29 12:30 ` [PATCH v2 15/17] i386: Fix NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14] Zhao Liu
2023-05-29 12:31 ` [PATCH v2 16/17] i386: Use CPUCacheInfo.share_level to encode " Zhao Liu
2023-05-29 12:31 ` [PATCH v2 17/17] i386: Add new property to control L2 cache topo in CPUID.04H Zhao Liu
2023-06-13 7:57 ` [PATCH v2 00/17] Support smp.clusters for x86 Zhao Liu
2023-06-14 1:59 ` Ma, Yongwei
2023-06-22 20:14 ` Michael S. Tsirkin
2023-06-28 1:18 ` Zhao Liu
2023-07-10 18:42 ` Michael S. Tsirkin
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