From: Frederic Barrat <fbarrat@linux.ibm.com>
To: clg@kaod.org, danielhb413@gmail.com, qemu-ppc@nongnu.org,
qemu-devel@nongnu.org
Subject: [PATCH 0/4] Various xive fixes
Date: Tue, 30 May 2023 18:11:25 +0200 [thread overview]
Message-ID: <20230530161129.313258-1-fbarrat@linux.ibm.com> (raw)
A set of small fixes for the interrupt controller (xive2) on P10.
Frederic Barrat (4):
pnv/xive2: Add definition for TCTXT Config register
pnv/xive2: Add definition for the ESB cache configuration register
pnv/xive2: Allow writes to the Physical Thread Enable registers
pnv/xive2: Handle TIMA access through all ports
hw/intc/pnv_xive2.c | 20 +++++++++++++++++++-
hw/intc/pnv_xive2_regs.h | 8 ++++++++
hw/intc/xive.c | 18 ++++++++++++++++++
3 files changed, 45 insertions(+), 1 deletion(-)
--
2.40.1
next reply other threads:[~2023-05-30 16:13 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-30 16:11 Frederic Barrat [this message]
2023-05-30 16:11 ` [PATCH 1/4] pnv/xive2: Add definition for TCTXT Config register Frederic Barrat
2023-05-30 16:31 ` Cédric Le Goater
2023-05-30 18:01 ` Frederic Barrat
2023-05-30 16:11 ` [PATCH 2/4] pnv/xive2: Add definition for the ESB cache configuration register Frederic Barrat
2023-05-30 16:32 ` Cédric Le Goater
2023-05-30 16:11 ` [PATCH 3/4] pnv/xive2: Allow writes to the Physical Thread Enable registers Frederic Barrat
2023-05-30 16:37 ` Cédric Le Goater
2023-05-30 16:11 ` [PATCH 4/4] pnv/xive2: Handle TIMA access through all ports Frederic Barrat
2023-05-30 16:40 ` Cédric Le Goater
2023-05-30 16:49 ` Cédric Le Goater
2023-05-30 17:30 ` Frederic Barrat
2023-05-30 17:29 ` Frederic Barrat
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