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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org, Peter Maydell <peter.maydell@linaro.org>
Subject: [PATCH v3 01/20] target/arm: Add commentary for CPUARMState.exclusive_high
Date: Tue, 30 May 2023 12:14:19 -0700	[thread overview]
Message-ID: <20230530191438.411344-2-richard.henderson@linaro.org> (raw)
In-Reply-To: <20230530191438.411344-1-richard.henderson@linaro.org>

Document the meaning of exclusive_high in a big-endian context,
and why we can't change it now.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpu.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index d469a2637b..81c0df9c25 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -677,8 +677,16 @@ typedef struct CPUArchState {
         uint64_t zcr_el[4];   /* ZCR_EL[1-3] */
         uint64_t smcr_el[4];  /* SMCR_EL[1-3] */
     } vfp;
+
     uint64_t exclusive_addr;
     uint64_t exclusive_val;
+    /*
+     * Contains the 'val' for the second 64-bit register of LDXP, which comes
+     * from the higher address, not the high part of a complete 128-bit value.
+     * In some ways it might be more convenient to record the exclusive value
+     * as the low and high halves of a 128 bit data value, but the current
+     * semantics of these fields are baked into the migration format.
+     */
     uint64_t exclusive_high;
 
     /* iwMMXt coprocessor state.  */
-- 
2.34.1



  reply	other threads:[~2023-05-30 19:23 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-30 19:14 [PATCH v3 00/20] target/arm: Implement FEAT_LSE2 Richard Henderson
2023-05-30 19:14 ` Richard Henderson [this message]
2023-05-30 19:14 ` [PATCH v3 02/20] target/arm: Add feature test for FEAT_LSE2 Richard Henderson
2023-05-30 19:14 ` [PATCH v3 03/20] target/arm: Introduce finalize_memop_{atom,pair} Richard Henderson
2023-05-30 19:14 ` [PATCH v3 04/20] target/arm: Use tcg_gen_qemu_ld_i128 for LDXP Richard Henderson
2023-05-30 19:14 ` [PATCH v3 05/20] target/arm: Use tcg_gen_qemu_{st, ld}_i128 for do_fp_{st, ld} Richard Henderson
2023-05-30 19:14 ` [PATCH v3 06/20] target/arm: Use tcg_gen_qemu_st_i128 for STZG, STZ2G Richard Henderson
2023-05-30 19:14 ` [PATCH v3 07/20] target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r Richard Henderson
2023-05-30 19:14 ` [PATCH v3 08/20] target/arm: Sink gen_mte_check1 into load/store_exclusive Richard Henderson
2023-05-30 19:14 ` [PATCH v3 09/20] target/arm: Load/store integer pair with one tcg operation Richard Henderson
2023-05-30 19:14 ` [PATCH v3 10/20] target/arm: Hoist finalize_memop out of do_gpr_{ld, st} Richard Henderson
2023-05-30 19:14 ` [PATCH v3 11/20] target/arm: Hoist finalize_memop out of do_fp_{ld, st} Richard Henderson
2023-05-30 19:14 ` [PATCH v3 12/20] target/arm: Pass memop to gen_mte_check1* Richard Henderson
2023-05-30 19:14 ` [PATCH v3 13/20] target/arm: Pass single_memop to gen_mte_checkN Richard Henderson
2023-05-30 19:14 ` [PATCH v3 14/20] target/arm: Check alignment in helper_mte_check Richard Henderson
2023-05-30 19:14 ` [PATCH v3 15/20] target/arm: Add SCTLR.nAA to TBFLAG_A64 Richard Henderson
2023-05-30 19:14 ` [PATCH v3 16/20] target/arm: Relax ordered/atomic alignment checks for LSE2 Richard Henderson
2023-05-30 19:14 ` [PATCH v3 17/20] target/arm: Move mte check for store-exclusive Richard Henderson
2023-05-30 19:14 ` [PATCH v3 18/20] tests/tcg/aarch64: Use stz2g in mte-7.c Richard Henderson
2023-05-30 19:14 ` [PATCH v3 19/20] tests/tcg/multiarch: Adjust sigbus.c Richard Henderson
2023-05-30 19:14 ` [PATCH v3 20/20] target/arm: Enable FEAT_LSE2 for -cpu max Richard Henderson
2023-06-05 15:56 ` [PATCH v3 00/20] target/arm: Implement FEAT_LSE2 Peter Maydell

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