* [PATCH v3 1/3] hw/i2c: add smbus pec utility function
2023-05-31 11:47 [PATCH v3 0/3] hw/{i2c, nvme}: mctp endpoint, nvme management interface model Klaus Jensen
@ 2023-05-31 11:47 ` Klaus Jensen
2023-05-31 13:13 ` Jonathan Cameron via
2023-06-01 20:34 ` Philippe Mathieu-Daudé
2023-05-31 11:47 ` [PATCH v3 2/3] hw/i2c: add mctp core Klaus Jensen
` (2 subsequent siblings)
3 siblings, 2 replies; 10+ messages in thread
From: Klaus Jensen @ 2023-05-31 11:47 UTC (permalink / raw)
To: qemu-devel
Cc: Corey Minyard, Keith Busch, Jason Wang, Lior Weintraub,
Paolo Bonzini, Jeremy Kerr, qemu-arm, Matt Johnston,
Peter Delevoryas, Jonathan Cameron, qemu-block,
Cédric Le Goater, Klaus Jensen, Peter Maydell, Klaus Jensen,
gost.dev
From: Klaus Jensen <k.jensen@samsung.com>
Add i2c_smbus_pec() to calculate the SMBus Packet Error Code for a
message.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
---
hw/i2c/smbus_master.c | 28 ++++++++++++++++++++++++++++
include/hw/i2c/smbus_master.h | 2 ++
2 files changed, 30 insertions(+)
diff --git a/hw/i2c/smbus_master.c b/hw/i2c/smbus_master.c
index 6a53c34e70b7..47f9eb24e033 100644
--- a/hw/i2c/smbus_master.c
+++ b/hw/i2c/smbus_master.c
@@ -15,6 +15,34 @@
#include "hw/i2c/i2c.h"
#include "hw/i2c/smbus_master.h"
+static uint8_t crc8(uint16_t data)
+{
+#define POLY (0x1070U << 3)
+ int i;
+
+ for (i = 0; i < 8; i++) {
+ if (data & 0x8000) {
+ data = data ^ POLY;
+ }
+
+ data = data << 1;
+ }
+
+ return (uint8_t)(data >> 8);
+#undef POLY
+}
+
+uint8_t i2c_smbus_pec(uint8_t crc, uint8_t *buf, size_t len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ crc = crc8((crc ^ buf[i]) << 8);
+ }
+
+ return crc;
+}
+
/* Master device commands. */
int smbus_quick_command(I2CBus *bus, uint8_t addr, int read)
{
diff --git a/include/hw/i2c/smbus_master.h b/include/hw/i2c/smbus_master.h
index bb13bc423c22..d90f81767d86 100644
--- a/include/hw/i2c/smbus_master.h
+++ b/include/hw/i2c/smbus_master.h
@@ -27,6 +27,8 @@
#include "hw/i2c/i2c.h"
+uint8_t i2c_smbus_pec(uint8_t crc, uint8_t *buf, size_t len);
+
/* Master device commands. */
int smbus_quick_command(I2CBus *bus, uint8_t addr, int read);
int smbus_receive_byte(I2CBus *bus, uint8_t addr);
--
2.40.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v3 1/3] hw/i2c: add smbus pec utility function
2023-05-31 11:47 ` [PATCH v3 1/3] hw/i2c: add smbus pec utility function Klaus Jensen
@ 2023-05-31 13:13 ` Jonathan Cameron via
2023-06-01 20:34 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 10+ messages in thread
From: Jonathan Cameron via @ 2023-05-31 13:13 UTC (permalink / raw)
To: Klaus Jensen
Cc: qemu-devel, Corey Minyard, Keith Busch, Jason Wang,
Lior Weintraub, Paolo Bonzini, Jeremy Kerr, qemu-arm,
Matt Johnston, Peter Delevoryas, qemu-block,
Cédric Le Goater, Klaus Jensen, Peter Maydell, gost.dev
On Wed, 31 May 2023 13:47:42 +0200
Klaus Jensen <its@irrelevant.dk> wrote:
> From: Klaus Jensen <k.jensen@samsung.com>
>
> Add i2c_smbus_pec() to calculate the SMBus Packet Error Code for a
> message.
>
> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
LGTM
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
> hw/i2c/smbus_master.c | 28 ++++++++++++++++++++++++++++
> include/hw/i2c/smbus_master.h | 2 ++
> 2 files changed, 30 insertions(+)
>
> diff --git a/hw/i2c/smbus_master.c b/hw/i2c/smbus_master.c
> index 6a53c34e70b7..47f9eb24e033 100644
> --- a/hw/i2c/smbus_master.c
> +++ b/hw/i2c/smbus_master.c
> @@ -15,6 +15,34 @@
> #include "hw/i2c/i2c.h"
> #include "hw/i2c/smbus_master.h"
>
> +static uint8_t crc8(uint16_t data)
> +{
> +#define POLY (0x1070U << 3)
> + int i;
> +
> + for (i = 0; i < 8; i++) {
> + if (data & 0x8000) {
> + data = data ^ POLY;
> + }
> +
> + data = data << 1;
> + }
> +
> + return (uint8_t)(data >> 8);
> +#undef POLY
> +}
> +
> +uint8_t i2c_smbus_pec(uint8_t crc, uint8_t *buf, size_t len)
> +{
> + int i;
> +
> + for (i = 0; i < len; i++) {
> + crc = crc8((crc ^ buf[i]) << 8);
> + }
> +
> + return crc;
> +}
> +
> /* Master device commands. */
> int smbus_quick_command(I2CBus *bus, uint8_t addr, int read)
> {
> diff --git a/include/hw/i2c/smbus_master.h b/include/hw/i2c/smbus_master.h
> index bb13bc423c22..d90f81767d86 100644
> --- a/include/hw/i2c/smbus_master.h
> +++ b/include/hw/i2c/smbus_master.h
> @@ -27,6 +27,8 @@
>
> #include "hw/i2c/i2c.h"
>
> +uint8_t i2c_smbus_pec(uint8_t crc, uint8_t *buf, size_t len);
> +
> /* Master device commands. */
> int smbus_quick_command(I2CBus *bus, uint8_t addr, int read);
> int smbus_receive_byte(I2CBus *bus, uint8_t addr);
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH v3 1/3] hw/i2c: add smbus pec utility function
2023-05-31 11:47 ` [PATCH v3 1/3] hw/i2c: add smbus pec utility function Klaus Jensen
2023-05-31 13:13 ` Jonathan Cameron via
@ 2023-06-01 20:34 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 10+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-06-01 20:34 UTC (permalink / raw)
To: Klaus Jensen, qemu-devel
Cc: Corey Minyard, Keith Busch, Jason Wang, Lior Weintraub,
Paolo Bonzini, Jeremy Kerr, qemu-arm, Matt Johnston,
Peter Delevoryas, Jonathan Cameron, qemu-block,
Cédric Le Goater, Klaus Jensen, Peter Maydell, gost.dev
On 31/5/23 13:47, Klaus Jensen wrote:
> From: Klaus Jensen <k.jensen@samsung.com>
>
> Add i2c_smbus_pec() to calculate the SMBus Packet Error Code for a
> message.
>
> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
> ---
> hw/i2c/smbus_master.c | 28 ++++++++++++++++++++++++++++
> include/hw/i2c/smbus_master.h | 2 ++
> 2 files changed, 30 insertions(+)
>
> diff --git a/hw/i2c/smbus_master.c b/hw/i2c/smbus_master.c
> index 6a53c34e70b7..47f9eb24e033 100644
> --- a/hw/i2c/smbus_master.c
> +++ b/hw/i2c/smbus_master.c
> @@ -15,6 +15,34 @@
> #include "hw/i2c/i2c.h"
> #include "hw/i2c/smbus_master.h"
>
> +static uint8_t crc8(uint16_t data)
> +{
> +#define POLY (0x1070U << 3)
static const unsigned crc8_poly = ..., but why not inline the single use?
data ^= 0x1070U << 3;
and
data <<= 1;
> + int i;
> +
> + for (i = 0; i < 8; i++) {
> + if (data & 0x8000) {
> + data = data ^ POLY;
> + }
> +
> + data = data << 1;
> + }
> +
> + return (uint8_t)(data >> 8);
> +#undef POLY
> +}
We have "qemu/crc32c.h", maybe we could have a similar crc8.h. Just
wondering...
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v3 2/3] hw/i2c: add mctp core
2023-05-31 11:47 [PATCH v3 0/3] hw/{i2c, nvme}: mctp endpoint, nvme management interface model Klaus Jensen
2023-05-31 11:47 ` [PATCH v3 1/3] hw/i2c: add smbus pec utility function Klaus Jensen
@ 2023-05-31 11:47 ` Klaus Jensen
2023-05-31 14:59 ` Jonathan Cameron via
2023-05-31 11:47 ` [PATCH v3 3/3] hw/nvme: add nvme management interface model Klaus Jensen
2023-06-01 19:42 ` [PATCH v3 0/3] hw/{i2c, nvme}: mctp endpoint, " Corey Minyard
3 siblings, 1 reply; 10+ messages in thread
From: Klaus Jensen @ 2023-05-31 11:47 UTC (permalink / raw)
To: qemu-devel
Cc: Corey Minyard, Keith Busch, Jason Wang, Lior Weintraub,
Paolo Bonzini, Jeremy Kerr, qemu-arm, Matt Johnston,
Peter Delevoryas, Jonathan Cameron, qemu-block,
Cédric Le Goater, Klaus Jensen, Peter Maydell, Klaus Jensen,
gost.dev
From: Klaus Jensen <k.jensen@samsung.com>
Add an abstract MCTP over I2C endpoint model. This implements MCTP
control message handling as well as handling the actual I2C transport
(packetization).
Devices are intended to derive from this and implement the class
methods.
Parts of this implementation is inspired by code[1] previously posted by
Jonathan Cameron.
Squashed a fix[2] from Matt Johnston.
[1]: https://lore.kernel.org/qemu-devel/20220520170128.4436-1-Jonathan.Cameron@huawei.com/
[2]: https://lore.kernel.org/qemu-devel/20221121080445.GA29062@codeconstruct.com.au/
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
---
MAINTAINERS | 7 +
hw/arm/Kconfig | 1 +
hw/i2c/Kconfig | 4 +
hw/i2c/mctp.c | 398 ++++++++++++++++++++++++++++++++++++++++++
hw/i2c/meson.build | 1 +
hw/i2c/trace-events | 13 ++
include/hw/i2c/mctp.h | 137 +++++++++++++++
include/net/mctp.h | 28 +++
8 files changed, 589 insertions(+)
create mode 100644 hw/i2c/mctp.c
create mode 100644 include/hw/i2c/mctp.h
create mode 100644 include/net/mctp.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 4b025a7b63e2..80d440b21ecb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3354,6 +3354,13 @@ F: tests/qtest/adm1272-test.c
F: tests/qtest/max34451-test.c
F: tests/qtest/isl_pmbus_vr-test.c
+MCTP I2C Transport
+M: Klaus Jensen <k.jensen@samsung.com>
+S: Maintained
+F: hw/i2c/mctp.c
+F: include/hw/i2c/mctp.h
+F: include/net/mctp.h
+
Firmware schema specifications
M: Philippe Mathieu-Daudé <philmd@linaro.org>
R: Daniel P. Berrange <berrange@redhat.com>
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index acc4371a4ae8..eb4559ef2ba4 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -528,6 +528,7 @@ config ASPEED_SOC
select DS1338
select FTGMAC100
select I2C
+ select MCTP_I2C
select DPS310
select PCA9552
select SERIAL
diff --git a/hw/i2c/Kconfig b/hw/i2c/Kconfig
index 14886b35dac2..3415e8421ab1 100644
--- a/hw/i2c/Kconfig
+++ b/hw/i2c/Kconfig
@@ -45,3 +45,7 @@ config PCA954X
config PMBUS
bool
select SMBUS
+
+config MCTP_I2C
+ bool
+ select I2C
diff --git a/hw/i2c/mctp.c b/hw/i2c/mctp.c
new file mode 100644
index 000000000000..c0cf2e4806e8
--- /dev/null
+++ b/hw/i2c/mctp.c
@@ -0,0 +1,398 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * SPDX-FileCopyrightText: Copyright (c) 2022 Samsung Electronics Co., Ltd.
+ * SPDX-FileContributor: Klaus Jensen <k.jensen@samsung.com>
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/main-loop.h"
+
+#include "hw/qdev-properties.h"
+#include "hw/i2c/i2c.h"
+#include "hw/i2c/smbus_master.h"
+#include "hw/i2c/mctp.h"
+
+#include "trace.h"
+
+/* DSP0237 1.2.0, Figure 1 */
+typedef struct MCTPI2CPacketHeader {
+ uint8_t dest;
+#define MCTP_I2C_COMMAND_CODE 0xf
+ uint8_t command_code;
+ uint8_t byte_count;
+ uint8_t source;
+} MCTPI2CPacketHeader;
+
+typedef struct MCTPI2CPacket {
+ MCTPI2CPacketHeader i2c;
+ MCTPPacket mctp;
+} MCTPI2CPacket;
+
+#define i2c_mctp_payload(buf) (buf + offsetof(MCTPI2CPacket, mctp.payload))
+
+/* DSP0236 1.3.0, Figure 20 */
+typedef struct MCTPControlMessage {
+#define MCTP_MESSAGE_TYPE_CONTROL 0x0
+ uint8_t type;
+#define MCTP_CONTROL_FLAGS_RQ (1 << 7)
+#define MCTP_CONTROL_FLAGS_D (1 << 6)
+ uint8_t flags;
+ uint8_t command_code;
+ uint8_t data[];
+} MCTPControlMessage;
+
+enum MCTPControlCommandCodes {
+ MCTP_CONTROL_SET_EID = 0x01,
+ MCTP_CONTROL_GET_EID = 0x02,
+ MCTP_CONTROL_GET_VERSION = 0x04,
+ MCTP_CONTROL_GET_MESSAGE_TYPE_SUPPORT = 0x05,
+};
+
+#define MCTP_CONTROL_ERROR_UNSUPPORTED_CMD 0x5
+
+#define i2c_mctp_control_data(buf) \
+ (i2c_mctp_payload(buf) + offsetof(MCTPControlMessage, data))
+
+
+void i2c_mctp_schedule_send(MCTPI2CEndpoint *mctp)
+{
+ I2CBus *i2c = I2C_BUS(qdev_get_parent_bus(DEVICE(mctp)));
+
+ mctp->tx.state = I2C_MCTP_STATE_TX_START_SEND;
+
+ i2c_bus_master(i2c, mctp->tx.bh);
+}
+
+static void i2c_mctp_tx(void *opaque)
+{
+ DeviceState *dev = DEVICE(opaque);
+ I2CBus *i2c = I2C_BUS(qdev_get_parent_bus(dev));
+ I2CSlave *slave = I2C_SLAVE(dev);
+ MCTPI2CEndpoint *mctp = MCTP_I2C_ENDPOINT(dev);
+ MCTPI2CEndpointClass *mc = MCTP_I2C_ENDPOINT_GET_CLASS(mctp);
+ MCTPI2CPacket *pkt = (MCTPI2CPacket *)mctp->buffer;
+ uint8_t flags = 0;
+
+ switch (mctp->tx.state) {
+ case I2C_MCTP_STATE_TX_SEND_BYTE:
+ if (mctp->pos < mctp->len) {
+ uint8_t byte = mctp->buffer[mctp->pos];
+
+ trace_i2c_mctp_tx_send_byte(mctp->pos, byte);
+
+ /* send next byte */
+ i2c_send_async(i2c, byte);
+
+ mctp->pos++;
+
+ break;
+ }
+
+ /* packet sent */
+ i2c_end_transfer(i2c);
+
+ /* end of any control data */
+ mctp->len = 0;
+
+ /* fall through */
+
+ case I2C_MCTP_STATE_TX_START_SEND:
+ if (mctp->tx.is_control) {
+ /* packet payload is already in buffer */
+ flags |= MCTP_H_FLAGS_SOM | MCTP_H_FLAGS_EOM;
+ } else {
+ const uint8_t *payload;
+
+ /* get message bytes from derived device */
+ mctp->len = mc->get_buf(mctp, &payload, I2C_MCTP_MAXMTU, &flags);
+ assert(mctp->len <= I2C_MCTP_MAXMTU);
+
+ memcpy(pkt->mctp.payload, payload, mctp->len);
+ }
+
+ if (!mctp->len) {
+ trace_i2c_mctp_tx_done();
+
+ /* no more packets needed; release the bus */
+ i2c_bus_release(i2c);
+
+ mctp->state = I2C_MCTP_STATE_IDLE;
+ mctp->tx.is_control = false;
+
+ break;
+ }
+
+ mctp->state = I2C_MCTP_STATE_TX;
+
+ pkt->i2c = (MCTPI2CPacketHeader) {
+ .dest = mctp->tx.addr & ~0x1,
+ .command_code = MCTP_I2C_COMMAND_CODE,
+ .byte_count = 5 + mctp->len,
+ .source = slave->address << 1 | 0x1,
+ };
+
+ pkt->mctp.hdr = (MCTPPacketHeader) {
+ .version = 0x1,
+ .eid.dest = mctp->tx.eid,
+ .eid.source = mctp->my_eid,
+ .flags = flags | (mctp->tx.pktseq++ & 0x3) << 4 | mctp->tx.flags,
+ };
+
+ mctp->len += sizeof(MCTPI2CPacket);
+ assert(mctp->len < I2C_MCTP_MAX_LENGTH);
+
+ mctp->buffer[mctp->len] = i2c_smbus_pec(0, mctp->buffer, mctp->len);
+ mctp->len++;
+
+ trace_i2c_mctp_tx_start_send(mctp->len);
+
+ i2c_start_send_async(i2c, pkt->i2c.dest >> 1);
+
+ /* already "sent" the destination slave address */
+ mctp->pos = 1;
+
+ mctp->tx.state = I2C_MCTP_STATE_TX_SEND_BYTE;
+
+ break;
+ }
+}
+
+static void i2c_mctp_handle_control_set_eid(MCTPI2CEndpoint *mctp, uint8_t eid)
+{
+ mctp->my_eid = eid;
+
+ uint8_t buf[] = {
+ 0x0, 0x0, eid, 0x0,
+ };
+
+ memcpy(i2c_mctp_control_data(mctp->buffer), buf, sizeof(buf));
+ mctp->len += sizeof(buf);
+}
+
+static void i2c_mctp_handle_control_get_eid(MCTPI2CEndpoint *mctp)
+{
+ uint8_t buf[] = {
+ 0x0, mctp->my_eid, 0x0, 0x0,
+ };
+
+ memcpy(i2c_mctp_control_data(mctp->buffer), buf, sizeof(buf));
+ mctp->len += sizeof(buf);
+}
+
+static void i2c_mctp_handle_control_get_version(MCTPI2CEndpoint *mctp)
+{
+ uint8_t buf[] = {
+ 0x0, 0x1, 0x0, 0x1, 0x3, 0x1,
+ };
+
+ memcpy(i2c_mctp_control_data(mctp->buffer), buf, sizeof(buf));
+ mctp->len += sizeof(buf);
+}
+
+static void i2c_mctp_handle_get_message_type_support(MCTPI2CEndpoint *mctp)
+{
+ MCTPI2CEndpointClass *mc = MCTP_I2C_ENDPOINT_GET_CLASS(mctp);
+ const uint8_t *types;
+ size_t len;
+
+ len = mc->get_types(mctp, &types);
+ assert(len > 0 && len <= MCTP_BASELINE_MTU - mctp->len);
+
+ memcpy(i2c_mctp_control_data(mctp->buffer), types, len);
+ mctp->len += len;
+}
+
+static void i2c_mctp_handle_control(MCTPI2CEndpoint *mctp)
+{
+ MCTPControlMessage *msg = (MCTPControlMessage *)i2c_mctp_payload(mctp->buffer);
+
+ /* clear Rq/D */
+ msg->flags &= ~(MCTP_CONTROL_FLAGS_RQ | MCTP_CONTROL_FLAGS_D);
+
+ mctp->len = sizeof(MCTPControlMessage);
+
+ trace_i2c_mctp_handle_control(msg->command_code);
+
+ switch (msg->command_code) {
+ case MCTP_CONTROL_SET_EID:
+ i2c_mctp_handle_control_set_eid(mctp, msg->data[1]);
+ break;
+
+ case MCTP_CONTROL_GET_EID:
+ i2c_mctp_handle_control_get_eid(mctp);
+ break;
+
+ case MCTP_CONTROL_GET_VERSION:
+ i2c_mctp_handle_control_get_version(mctp);
+ break;
+
+ case MCTP_CONTROL_GET_MESSAGE_TYPE_SUPPORT:
+ i2c_mctp_handle_get_message_type_support(mctp);
+ break;
+
+ default:
+ trace_i2c_mctp_unhandled_control(msg->command_code);
+
+ msg->data[0] = MCTP_CONTROL_ERROR_UNSUPPORTED_CMD;
+ mctp->len++;
+
+ break;
+ }
+
+ assert(mctp->len <= MCTP_BASELINE_MTU);
+
+ i2c_mctp_schedule_send(mctp);
+}
+
+static int i2c_mctp_event_cb(I2CSlave *i2c, enum i2c_event event)
+{
+ MCTPI2CEndpoint *mctp = MCTP_I2C_ENDPOINT(i2c);
+ MCTPI2CEndpointClass *mc = MCTP_I2C_ENDPOINT_GET_CLASS(mctp);
+ MCTPI2CPacket *pkt = (MCTPI2CPacket *)mctp->buffer;
+ size_t payload_len;
+ uint8_t pec;
+
+ switch (event) {
+ case I2C_START_SEND:
+ if (mctp->state == I2C_MCTP_STATE_IDLE) {
+ mctp->state = I2C_MCTP_STATE_RX_STARTED;
+ } else if (mctp->state != I2C_MCTP_STATE_RX) {
+ return -1;
+ }
+
+ /* the i2c core eats the slave address, so put it back in */
+ pkt->i2c.dest = i2c->address << 1;
+ mctp->len = 1;
+
+ return 0;
+
+ case I2C_FINISH:
+ if (mctp->len < sizeof(MCTPI2CPacket) + 1) {
+ trace_i2c_mctp_drop_short_packet(mctp->len);
+ goto drop;
+ }
+
+ payload_len = mctp->len - (1 + offsetof(MCTPI2CPacket, mctp.payload));
+
+ if (pkt->i2c.byte_count + 3 != mctp->len - 1) {
+ trace_i2c_mctp_drop_invalid_length(pkt->i2c.byte_count + 3,
+ mctp->len - 1);
+ goto drop;
+ }
+
+ pec = i2c_smbus_pec(0, mctp->buffer, mctp->len - 1);
+ if (mctp->buffer[mctp->len - 1] != pec) {
+ trace_i2c_mctp_drop_invalid_pec(mctp->buffer[mctp->len - 1], pec);
+ goto drop;
+ }
+
+ if (!(pkt->mctp.hdr.eid.dest == mctp->my_eid ||
+ pkt->mctp.hdr.eid.dest == 0)) {
+ trace_i2c_mctp_drop_invalid_eid(pkt->mctp.hdr.eid.dest,
+ mctp->my_eid);
+ goto drop;
+ }
+
+ if (pkt->mctp.hdr.flags & MCTP_H_FLAGS_SOM) {
+ mctp->tx.is_control = false;
+
+ if (mctp->state == I2C_MCTP_STATE_RX) {
+ mc->reset(mctp);
+ }
+
+ mctp->state = I2C_MCTP_STATE_RX;
+
+ mctp->tx.addr = pkt->i2c.source;
+ mctp->tx.eid = pkt->mctp.hdr.eid.source;
+ mctp->tx.flags = pkt->mctp.hdr.flags & 0x7;
+ mctp->tx.pktseq = (pkt->mctp.hdr.flags >> 4) & 0x3;
+
+ if ((pkt->mctp.payload[0] & 0x7f) == MCTP_MESSAGE_TYPE_CONTROL) {
+ mctp->tx.is_control = true;
+
+ i2c_mctp_handle_control(mctp);
+
+ return 0;
+ }
+ } else if (mctp->state == I2C_MCTP_STATE_RX_STARTED) {
+ trace_i2c_mctp_drop_expected_som();
+ goto drop;
+ } else if (((pkt->mctp.hdr.flags >> 4) & 0x3) != (++mctp->tx.pktseq & 0x3)) {
+ trace_i2c_mctp_drop_invalid_pktseq((pkt->mctp.hdr.flags >> 4) & 0x3,
+ mctp->tx.pktseq & 0x3);
+ goto drop;
+ }
+
+ mc->put_buf(mctp, i2c_mctp_payload(mctp->buffer), payload_len);
+
+ if (pkt->mctp.hdr.flags & MCTP_H_FLAGS_EOM) {
+ mc->handle(mctp);
+ mctp->state = I2C_MCTP_STATE_WAIT_TX;
+ }
+
+ return 0;
+
+ default:
+ return -1;
+ }
+
+drop:
+ mc->reset(mctp);
+
+ mctp->state = I2C_MCTP_STATE_IDLE;
+
+ return 0;
+}
+
+static int i2c_mctp_send_cb(I2CSlave *i2c, uint8_t data)
+{
+ MCTPI2CEndpoint *mctp = MCTP_I2C_ENDPOINT(i2c);
+
+ if (mctp->len < I2C_MCTP_MAX_LENGTH) {
+ mctp->buffer[mctp->len++] = data;
+ return 0;
+ }
+
+ return -1;
+}
+
+static void i2c_mctp_instance_init(Object *obj)
+{
+ MCTPI2CEndpoint *mctp = MCTP_I2C_ENDPOINT(obj);
+
+ mctp->tx.bh = qemu_bh_new(i2c_mctp_tx, mctp);
+}
+
+static Property mctp_i2c_props[] = {
+ DEFINE_PROP_UINT8("eid", MCTPI2CEndpoint, my_eid, 0x9),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void i2c_mctp_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ I2CSlaveClass *k = I2C_SLAVE_CLASS(oc);
+
+ k->event = i2c_mctp_event_cb;
+ k->send = i2c_mctp_send_cb;
+
+ device_class_set_props(dc, mctp_i2c_props);
+}
+
+static const TypeInfo i2c_mctp_info = {
+ .name = TYPE_MCTP_I2C_ENDPOINT,
+ .parent = TYPE_I2C_SLAVE,
+ .abstract = true,
+ .instance_init = i2c_mctp_instance_init,
+ .instance_size = sizeof(MCTPI2CEndpoint),
+ .class_init = i2c_mctp_class_init,
+ .class_size = sizeof(MCTPI2CEndpointClass),
+};
+
+static void register_types(void)
+{
+ type_register_static(&i2c_mctp_info);
+}
+
+type_init(register_types)
diff --git a/hw/i2c/meson.build b/hw/i2c/meson.build
index 3996564c25c6..fd1f9022fd96 100644
--- a/hw/i2c/meson.build
+++ b/hw/i2c/meson.build
@@ -1,5 +1,6 @@
i2c_ss = ss.source_set()
i2c_ss.add(when: 'CONFIG_I2C', if_true: files('core.c'))
+i2c_ss.add(when: 'CONFIG_MCTP_I2C', if_true: files('mctp.c'))
i2c_ss.add(when: 'CONFIG_SMBUS', if_true: files('smbus_slave.c', 'smbus_master.c'))
i2c_ss.add(when: 'CONFIG_ACPI_SMBUS', if_true: files('pm_smbus.c'))
i2c_ss.add(when: 'CONFIG_ACPI_ICH9', if_true: files('smbus_ich9.c'))
diff --git a/hw/i2c/trace-events b/hw/i2c/trace-events
index 8e88aa24c1ac..bc1a7176ef67 100644
--- a/hw/i2c/trace-events
+++ b/hw/i2c/trace-events
@@ -45,3 +45,16 @@ npcm7xx_smbus_recv_fifo(const char *id, uint8_t received, uint8_t expected) "%s
pca954x_write_bytes(uint8_t value) "PCA954X write data: 0x%02x"
pca954x_read_data(uint8_t value) "PCA954X read data: 0x%02x"
+
+# mctp.c
+i2c_mctp_tx_start_send(size_t len) "len %zu"
+i2c_mctp_tx_send_byte(size_t pos, uint8_t byte) "pos %zu byte 0x%"PRIx8""
+i2c_mctp_tx_done(void) "packet sent"
+i2c_mctp_handle_control(uint8_t command) "command 0x%"PRIx8""
+i2c_mctp_unhandled_control(uint8_t command) "command 0x%"PRIx8""
+i2c_mctp_drop_invalid_length(unsigned byte_count, size_t expected) "byte_count %u expected %zu"
+i2c_mctp_drop_invalid_pec(uint8_t pec, uint8_t expected) "pec 0x%"PRIx8" expected 0x%"PRIx8""
+i2c_mctp_drop_invalid_eid(uint8_t eid, uint8_t expected) "eid 0x%"PRIx8" expected 0x%"PRIx8""
+i2c_mctp_drop_invalid_pktseq(uint8_t pktseq, uint8_t expected) "pktseq 0x%"PRIx8" expected 0x%"PRIx8""
+i2c_mctp_drop_short_packet(size_t len) "len %zu"
+i2c_mctp_drop_expected_som(void) ""
diff --git a/include/hw/i2c/mctp.h b/include/hw/i2c/mctp.h
new file mode 100644
index 000000000000..ea97792e8d43
--- /dev/null
+++ b/include/hw/i2c/mctp.h
@@ -0,0 +1,137 @@
+#ifndef QEMU_I2C_MCTP_H
+#define QEMU_I2C_MCTP_H
+
+#include "qom/object.h"
+#include "hw/qdev-core.h"
+#include "net/mctp.h"
+
+#define TYPE_MCTP_I2C_ENDPOINT "mctp-i2c-endpoint"
+OBJECT_DECLARE_TYPE(MCTPI2CEndpoint, MCTPI2CEndpointClass, MCTP_I2C_ENDPOINT)
+
+struct MCTPI2CEndpointClass {
+ I2CSlaveClass parent_class;
+
+ /**
+ *
+ * put_buf() - receive incoming message fragment
+ *
+ * Must returns 0 for succes or -1 for error.
+ */
+ int (*put_buf)(MCTPI2CEndpoint *mctp, uint8_t *buf, size_t len);
+
+ /**
+ * get_buf() - provide pointer to message fragment
+ *
+ * Called by the mctp subsystem to request a pointer to the next message
+ * fragment. The implementation must advance its internal position such
+ * that successive calls returns the next fragments.
+ *
+ * Must return the number of bytes available.
+ */
+ size_t (*get_buf)(MCTPI2CEndpoint *mctp, const uint8_t **buf,
+ size_t maxlen, uint8_t *mctp_flags);
+
+ /**
+ * handle() - handle an MCTP message
+ *
+ * Called by the mctp subsystem when a full message has been delivered and
+ * may be parsed and processed.
+ */
+ void (*handle)(MCTPI2CEndpoint *mctp);
+
+ /**
+ * reset() - reset internal state
+ *
+ * Called by the mctp subsystem in the event of some transport error.
+ * Implementation must reset its internal state and drop any fragments
+ * previously receieved.
+ */
+ void (*reset)(MCTPI2CEndpoint *mctp);
+
+ /**
+ * get_types() - provide supported mctp message types
+ *
+ * Must provide a buffer with a full MCTP supported message types payload
+ * (i.e. `0x0(SUCCESS),0x1(ONE),0x4(NMI)`).
+ *
+ * Returns the size of the response.
+ */
+ size_t (*get_types)(MCTPI2CEndpoint *mctp, const uint8_t **data);
+};
+
+/*
+ * Maximum value of the SMBus Block Write "Byte Count" field (8 bits).
+ *
+ * This is the count of bytes that follow the Byte Count field and up to, but
+ * not including, the PEC byte.
+ */
+#define I2C_MCTP_MAXBLOCK 255
+
+/*
+ * Maximum Transmission Unit under I2C.
+ *
+ * This is for the MCTP Packet Payload (255, subtracting the 4 byte MCTP Packet
+ * Header or the 1 byte MCTP/I2C piggy-backed source address).
+ */
+#define I2C_MCTP_MAXMTU (I2C_MCTP_MAXBLOCK - (sizeof(MCTPPacketHeader) + 1))
+
+/*
+ * Maximum length of an MCTP/I2C packet.
+ *
+ * This is the sum of the three I2C header bytes (Destination target address,
+ * Command Code and Byte Count), the maximum number of bytes in a message (255)
+ * and the 1 byte Packet Error Code.
+ */
+#define I2C_MCTP_MAX_LENGTH (3 + I2C_MCTP_MAXBLOCK + 1)
+
+/*
+ * Maximum length of an MCTP/I2C Control Message.
+ *
+ * This is the 64 byte MCTP Baseline Maximum Transmission Unit, adding the
+ * combined MCTP/I2C headers and the trailing 1 byte PEC.
+ */
+#define I2C_MCTP_CONTROL_MAX_LENGTH \
+ (sizeof(MCTPI2CPacket) + MCTP_BASELINE_MTU + 1)
+
+typedef enum {
+ I2C_MCTP_STATE_IDLE,
+ I2C_MCTP_STATE_RX_STARTED,
+ I2C_MCTP_STATE_RX,
+ I2C_MCTP_STATE_WAIT_TX,
+ I2C_MCTP_STATE_TX,
+} MCTPState;
+
+typedef enum {
+ I2C_MCTP_STATE_TX_START_SEND,
+ I2C_MCTP_STATE_TX_SEND_BYTE,
+} MCTPTxState;
+
+typedef struct MCTPI2CEndpoint {
+ I2CSlave parent_obj;
+ I2CBus *i2c;
+
+ MCTPState state;
+
+ /* mctp endpoint identifier */
+ uint8_t my_eid;
+
+ uint8_t buffer[I2C_MCTP_MAX_LENGTH];
+ uint64_t pos;
+ size_t len;
+
+ struct {
+ MCTPTxState state;
+ bool is_control;
+
+ uint8_t eid;
+ uint8_t addr;
+ uint8_t pktseq;
+ uint8_t flags;
+
+ QEMUBH *bh;
+ } tx;
+} MCTPI2CEndpoint;
+
+void i2c_mctp_schedule_send(MCTPI2CEndpoint *mctp);
+
+#endif /* QEMU_I2C_MCTP_H */
diff --git a/include/net/mctp.h b/include/net/mctp.h
new file mode 100644
index 000000000000..70b49235ddb2
--- /dev/null
+++ b/include/net/mctp.h
@@ -0,0 +1,28 @@
+#ifndef QEMU_MCTP_H
+#define QEMU_MCTP_H
+
+#define MCTP_BASELINE_MTU 64
+
+enum {
+ MCTP_H_FLAGS_EOM = 1 << 6,
+ MCTP_H_FLAGS_SOM = 1 << 7,
+};
+
+#define MCTP_MESSAGE_IC (1 << 7)
+
+/* DSP0236 1.3.0, Figure 4 */
+typedef struct MCTPPacketHeader {
+ uint8_t version;
+ struct {
+ uint8_t dest;
+ uint8_t source;
+ } eid;
+ uint8_t flags;
+} MCTPPacketHeader;
+
+typedef struct MCTPPacket {
+ MCTPPacketHeader hdr;
+ uint8_t payload[];
+} MCTPPacket;
+
+#endif /* QEMU_MCTP_H */
--
2.40.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v3 2/3] hw/i2c: add mctp core
2023-05-31 11:47 ` [PATCH v3 2/3] hw/i2c: add mctp core Klaus Jensen
@ 2023-05-31 14:59 ` Jonathan Cameron via
2023-05-31 15:04 ` Jonathan Cameron via
0 siblings, 1 reply; 10+ messages in thread
From: Jonathan Cameron via @ 2023-05-31 14:59 UTC (permalink / raw)
To: Klaus Jensen
Cc: qemu-devel, Corey Minyard, Keith Busch, Jason Wang,
Lior Weintraub, Paolo Bonzini, Jeremy Kerr, qemu-arm,
Matt Johnston, Peter Delevoryas, qemu-block,
Cédric Le Goater, Klaus Jensen, Peter Maydell, gost.dev
On Wed, 31 May 2023 13:47:43 +0200
Klaus Jensen <its@irrelevant.dk> wrote:
> From: Klaus Jensen <k.jensen@samsung.com>
>
> Add an abstract MCTP over I2C endpoint model. This implements MCTP
> control message handling as well as handling the actual I2C transport
> (packetization).
>
> Devices are intended to derive from this and implement the class
> methods.
>
> Parts of this implementation is inspired by code[1] previously posted by
> Jonathan Cameron.
>
> Squashed a fix[2] from Matt Johnston.
>
> [1]: https://lore.kernel.org/qemu-devel/20220520170128.4436-1-Jonathan.Cameron@huawei.com/
> [2]: https://lore.kernel.org/qemu-devel/20221121080445.GA29062@codeconstruct.com.au/
>
> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Hi Klaus,
A few minor comments inline.
With those tidied up feel free to add
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> +
> + if (pkt->mctp.hdr.flags & MCTP_H_FLAGS_SOM) {
> + mctp->tx.is_control = false;
> +
> + if (mctp->state == I2C_MCTP_STATE_RX) {
> + mc->reset(mctp);
> + }
> +
> + mctp->state = I2C_MCTP_STATE_RX;
> +
> + mctp->tx.addr = pkt->i2c.source;
> + mctp->tx.eid = pkt->mctp.hdr.eid.source;
> + mctp->tx.flags = pkt->mctp.hdr.flags & 0x7;
Maybe worth either defining that mask, or adding a comment that this
is copying the msg tag. Or rename flags...
> + mctp->tx.pktseq = (pkt->mctp.hdr.flags >> 4) & 0x3;
> +
> + if ((pkt->mctp.payload[0] & 0x7f) == MCTP_MESSAGE_TYPE_CONTROL) {
> + mctp->tx.is_control = true;
> +
> + i2c_mctp_handle_control(mctp);
> +
> + return 0;
> + }
> + } else if (mctp->state == I2C_MCTP_STATE_RX_STARTED) {
> + trace_i2c_mctp_drop_expected_som();
> + goto drop;
> + } else if (((pkt->mctp.hdr.flags >> 4) & 0x3) != (++mctp->tx.pktseq & 0x3)) {
> + trace_i2c_mctp_drop_invalid_pktseq((pkt->mctp.hdr.flags >> 4) & 0x3,
> + mctp->tx.pktseq & 0x3);
> + goto drop;
> + }
> +
> + mc->put_buf(mctp, i2c_mctp_payload(mctp->buffer), payload_len);
> +
> + if (pkt->mctp.hdr.flags & MCTP_H_FLAGS_EOM) {
> + mc->handle(mctp);
> + mctp->state = I2C_MCTP_STATE_WAIT_TX;
> + }
> +
> + return 0;
> +
> + default:
> + return -1;
> + }
> +
> +drop:
> + mc->reset(mctp);
> +
> + mctp->state = I2C_MCTP_STATE_IDLE;
> +
> + return 0;
> +}
> diff --git a/include/hw/i2c/mctp.h b/include/hw/i2c/mctp.h
> new file mode 100644
> index 000000000000..ea97792e8d43
> --- /dev/null
> +++ b/include/hw/i2c/mctp.h
...
> +struct MCTPI2CEndpointClass {
> + I2CSlaveClass parent_class;
> +
> + /**
> + *
> + * put_buf() - receive incoming message fragment
> + *
> + * Must returns 0 for succes or -1 for error.
> + */
> + int (*put_buf)(MCTPI2CEndpoint *mctp, uint8_t *buf, size_t len);
> +
> + /**
> + * get_buf() - provide pointer to message fragment
> + *
> + * Called by the mctp subsystem to request a pointer to the next message
> + * fragment. The implementation must advance its internal position such
> + * that successive calls returns the next fragments.
> + *
> + * Must return the number of bytes available.
> + */
> + size_t (*get_buf)(MCTPI2CEndpoint *mctp, const uint8_t **buf,
> + size_t maxlen, uint8_t *mctp_flags);
> +
> + /**
> + * handle() - handle an MCTP message
> + *
> + * Called by the mctp subsystem when a full message has been delivered and
> + * may be parsed and processed.
> + */
> + void (*handle)(MCTPI2CEndpoint *mctp);
> +
> + /**
> + * reset() - reset internal state
> + *
> + * Called by the mctp subsystem in the event of some transport error.
> + * Implementation must reset its internal state and drop any fragments
> + * previously receieved.
> + */
> + void (*reset)(MCTPI2CEndpoint *mctp);
> +
> + /**
> + * get_types() - provide supported mctp message types
> + *
> + * Must provide a buffer with a full MCTP supported message types payload
> + * (i.e. `0x0(SUCCESS),0x1(ONE),0x4(NMI)`).
ONE? Looks to be PLDM
Good to reference DSP0239 Management Component Transport Protocol (MCTP) IDs and Codes
which has the list.
> + *
> + * Returns the size of the response.
> + */
> + size_t (*get_types)(MCTPI2CEndpoint *mctp, const uint8_t **data);
> +};
> diff --git a/include/net/mctp.h b/include/net/mctp.h
> new file mode 100644
> index 000000000000..70b49235ddb2
> --- /dev/null
> +++ b/include/net/mctp.h
> @@ -0,0 +1,28 @@
> +#ifndef QEMU_MCTP_H
> +#define QEMU_MCTP_H
> +
> +#define MCTP_BASELINE_MTU 64
Ideally add a reference for this as well.
8.3.1 Baseline transmission unit in DSP0236 1.3.0
> +
> +enum {
> + MCTP_H_FLAGS_EOM = 1 << 6,
> + MCTP_H_FLAGS_SOM = 1 << 7,
Trivial: I'm not really seeing the enum here as useful vs
a pair of defines.
> +};
> +
> +#define MCTP_MESSAGE_IC (1 << 7)
> +
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH v3 2/3] hw/i2c: add mctp core
2023-05-31 14:59 ` Jonathan Cameron via
@ 2023-05-31 15:04 ` Jonathan Cameron via
0 siblings, 0 replies; 10+ messages in thread
From: Jonathan Cameron via @ 2023-05-31 15:04 UTC (permalink / raw)
To: Klaus Jensen
Cc: qemu-devel, Corey Minyard, Keith Busch, Jason Wang,
Lior Weintraub, Paolo Bonzini, Jeremy Kerr, qemu-arm,
Matt Johnston, Peter Delevoryas, qemu-block,
Cédric Le Goater, Klaus Jensen, Peter Maydell, gost.dev
On Wed, 31 May 2023 15:59:44 +0100
Jonathan Cameron <Jonathan.Cameron@Huawei.com> wrote:
> On Wed, 31 May 2023 13:47:43 +0200
> Klaus Jensen <its@irrelevant.dk> wrote:
>
> > From: Klaus Jensen <k.jensen@samsung.com>
> >
> > Add an abstract MCTP over I2C endpoint model. This implements MCTP
> > control message handling as well as handling the actual I2C transport
> > (packetization).
> >
> > Devices are intended to derive from this and implement the class
> > methods.
> >
> > Parts of this implementation is inspired by code[1] previously posted by
> > Jonathan Cameron.
> >
> > Squashed a fix[2] from Matt Johnston.
> >
> > [1]: https://lore.kernel.org/qemu-devel/20220520170128.4436-1-Jonathan.Cameron@huawei.com/
> > [2]: https://lore.kernel.org/qemu-devel/20221121080445.GA29062@codeconstruct.com.au/
> >
> > Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
> Hi Klaus,
>
> A few minor comments inline.
>
> With those tidied up feel free to add
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
>
>
> > +
> > + if (pkt->mctp.hdr.flags & MCTP_H_FLAGS_SOM) {
> > + mctp->tx.is_control = false;
> > +
> > + if (mctp->state == I2C_MCTP_STATE_RX) {
> > + mc->reset(mctp);
> > + }
> > +
> > + mctp->state = I2C_MCTP_STATE_RX;
> > +
> > + mctp->tx.addr = pkt->i2c.source;
> > + mctp->tx.eid = pkt->mctp.hdr.eid.source;
> > + mctp->tx.flags = pkt->mctp.hdr.flags & 0x7;
>
> Maybe worth either defining that mask, or adding a comment that this
> is copying the msg tag. Or rename flags...
>
>
> > + mctp->tx.pktseq = (pkt->mctp.hdr.flags >> 4) & 0x3;
> > +
> > + if ((pkt->mctp.payload[0] & 0x7f) == MCTP_MESSAGE_TYPE_CONTROL) {
> > + mctp->tx.is_control = true;
> > +
> > + i2c_mctp_handle_control(mctp);
> > +
> > + return 0;
> > + }
> > + } else if (mctp->state == I2C_MCTP_STATE_RX_STARTED) {
> > + trace_i2c_mctp_drop_expected_som();
> > + goto drop;
> > + } else if (((pkt->mctp.hdr.flags >> 4) & 0x3) != (++mctp->tx.pktseq & 0x3)) {
> > + trace_i2c_mctp_drop_invalid_pktseq((pkt->mctp.hdr.flags >> 4) & 0x3,
> > + mctp->tx.pktseq & 0x3);
> > + goto drop;
> > + }
> > +
> > + mc->put_buf(mctp, i2c_mctp_payload(mctp->buffer), payload_len);
> > +
> > + if (pkt->mctp.hdr.flags & MCTP_H_FLAGS_EOM) {
> > + mc->handle(mctp);
> > + mctp->state = I2C_MCTP_STATE_WAIT_TX;
> > + }
> > +
> > + return 0;
> > +
> > + default:
> > + return -1;
> > + }
> > +
> > +drop:
> > + mc->reset(mctp);
> > +
> > + mctp->state = I2C_MCTP_STATE_IDLE;
> > +
> > + return 0;
> > +}
>
>
> > diff --git a/include/hw/i2c/mctp.h b/include/hw/i2c/mctp.h
> > new file mode 100644
> > index 000000000000..ea97792e8d43
> > --- /dev/null
> > +++ b/include/hw/i2c/mctp.h
>
> ...
> > +struct MCTPI2CEndpointClass {
> > + I2CSlaveClass parent_class;
> > +
> > + /**
> > + *
> > + * put_buf() - receive incoming message fragment
> > + *
> > + * Must returns 0 for succes or -1 for error.
> > + */
> > + int (*put_buf)(MCTPI2CEndpoint *mctp, uint8_t *buf, size_t len);
> > +
> > + /**
> > + * get_buf() - provide pointer to message fragment
> > + *
> > + * Called by the mctp subsystem to request a pointer to the next message
> > + * fragment. The implementation must advance its internal position such
> > + * that successive calls returns the next fragments.
> > + *
> > + * Must return the number of bytes available.
> > + */
> > + size_t (*get_buf)(MCTPI2CEndpoint *mctp, const uint8_t **buf,
> > + size_t maxlen, uint8_t *mctp_flags);
> > +
> > + /**
> > + * handle() - handle an MCTP message
> > + *
> > + * Called by the mctp subsystem when a full message has been delivered and
> > + * may be parsed and processed.
> > + */
> > + void (*handle)(MCTPI2CEndpoint *mctp);
> > +
> > + /**
> > + * reset() - reset internal state
> > + *
> > + * Called by the mctp subsystem in the event of some transport error.
> > + * Implementation must reset its internal state and drop any fragments
> > + * previously receieved.
> > + */
> > + void (*reset)(MCTPI2CEndpoint *mctp);
> > +
> > + /**
> > + * get_types() - provide supported mctp message types
> > + *
> > + * Must provide a buffer with a full MCTP supported message types payload
> > + * (i.e. `0x0(SUCCESS),0x1(ONE),0x4(NMI)`).
>
> ONE? Looks to be PLDM
> Good to reference DSP0239 Management Component Transport Protocol (MCTP) IDs and Codes
> which has the list.
Ah. 0x1 is the length. Call it "type count" instead of ONE and make it obvious.
>
> > + *
> > + * Returns the size of the response.
> > + */
> > + size_t (*get_types)(MCTPI2CEndpoint *mctp, const uint8_t **data);
> > +};
>
> > diff --git a/include/net/mctp.h b/include/net/mctp.h
> > new file mode 100644
> > index 000000000000..70b49235ddb2
> > --- /dev/null
> > +++ b/include/net/mctp.h
> > @@ -0,0 +1,28 @@
> > +#ifndef QEMU_MCTP_H
> > +#define QEMU_MCTP_H
> > +
> > +#define MCTP_BASELINE_MTU 64
>
> Ideally add a reference for this as well.
>
> 8.3.1 Baseline transmission unit in DSP0236 1.3.0
> > +
> > +enum {
> > + MCTP_H_FLAGS_EOM = 1 << 6,
> > + MCTP_H_FLAGS_SOM = 1 << 7,
>
> Trivial: I'm not really seeing the enum here as useful vs
> a pair of defines.
>
> > +};
> > +
> > +#define MCTP_MESSAGE_IC (1 << 7)
> > +
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v3 3/3] hw/nvme: add nvme management interface model
2023-05-31 11:47 [PATCH v3 0/3] hw/{i2c, nvme}: mctp endpoint, nvme management interface model Klaus Jensen
2023-05-31 11:47 ` [PATCH v3 1/3] hw/i2c: add smbus pec utility function Klaus Jensen
2023-05-31 11:47 ` [PATCH v3 2/3] hw/i2c: add mctp core Klaus Jensen
@ 2023-05-31 11:47 ` Klaus Jensen
2023-05-31 15:39 ` Jonathan Cameron via
2023-06-01 19:42 ` [PATCH v3 0/3] hw/{i2c, nvme}: mctp endpoint, " Corey Minyard
3 siblings, 1 reply; 10+ messages in thread
From: Klaus Jensen @ 2023-05-31 11:47 UTC (permalink / raw)
To: qemu-devel
Cc: Corey Minyard, Keith Busch, Jason Wang, Lior Weintraub,
Paolo Bonzini, Jeremy Kerr, qemu-arm, Matt Johnston,
Peter Delevoryas, Jonathan Cameron, qemu-block,
Cédric Le Goater, Klaus Jensen, Peter Maydell, Klaus Jensen,
gost.dev
From: Klaus Jensen <k.jensen@samsung.com>
Add the 'nmi-i2c' device that emulates an NVMe Management Interface
controller.
Initial support is very basic (Read NMI DS, Configuration Get).
This is based on previously posted code by Padmakar Kalghatgi, Arun
Kumar Agasar and Saurav Kumar.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
---
hw/nvme/meson.build | 1 +
hw/nvme/nmi-i2c.c | 367 +++++++++++++++++++++++++++++++++++++++++++
hw/nvme/trace-events | 6 +
3 files changed, 374 insertions(+)
create mode 100644 hw/nvme/nmi-i2c.c
diff --git a/hw/nvme/meson.build b/hw/nvme/meson.build
index 3cf40046eea9..b231e3fa12c2 100644
--- a/hw/nvme/meson.build
+++ b/hw/nvme/meson.build
@@ -1 +1,2 @@
softmmu_ss.add(when: 'CONFIG_NVME_PCI', if_true: files('ctrl.c', 'dif.c', 'ns.c', 'subsys.c'))
+softmmu_ss.add(when: 'CONFIG_MCTP_I2C', if_true: files('nmi-i2c.c'))
diff --git a/hw/nvme/nmi-i2c.c b/hw/nvme/nmi-i2c.c
new file mode 100644
index 000000000000..38e43e48fa51
--- /dev/null
+++ b/hw/nvme/nmi-i2c.c
@@ -0,0 +1,367 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * SPDX-FileCopyrightText: Copyright (c) 2022 Samsung Electronics Co., Ltd.
+ *
+ * SPDX-FileContributor: Padmakar Kalghatgi <p.kalghatgi@samsung.com>
+ * SPDX-FileContributor: Arun Kumar Agasar <arun.kka@samsung.com>
+ * SPDX-FileContributor: Saurav Kumar <saurav.29@partner.samsung.com>
+ * SPDX-FileContributor: Klaus Jensen <k.jensen@samsung.com>
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/crc32c.h"
+#include "hw/i2c/i2c.h"
+#include "hw/registerfields.h"
+#include "hw/i2c/mctp.h"
+#include "trace.h"
+
+#define MCTP_MESSAGE_TYPE_NMI 0x4
+
+#define NMI_MAX_MESSAGE_LENGTH 4224
+
+#define TYPE_NMI_I2C_DEVICE "nmi-i2c"
+OBJECT_DECLARE_SIMPLE_TYPE(NMIDevice, NMI_I2C_DEVICE)
+
+typedef struct NMIDevice {
+ MCTPI2CEndpoint mctp;
+
+ uint8_t buffer[NMI_MAX_MESSAGE_LENGTH];
+ uint8_t scratch[NMI_MAX_MESSAGE_LENGTH];
+
+ size_t len;
+ int64_t pos;
+} NMIDevice;
+
+FIELD(NMI_NMP, ROR, 7, 1)
+FIELD(NMI_NMP, NMIMT, 3, 4)
+
+#define NMI_NMP_NMIMT_NMI_CMD 0x1
+#define NMI_NMP_NMIMT_NM_ADMIN 0x2
+
+typedef struct NMIMessage {
+ uint8_t mctpd;
+ uint8_t nmp;
+ uint8_t rsvd2[2];
+ uint8_t payload[]; /* includes the Message Integrity Check */
+} NMIMessage;
+
+typedef struct NMIRequest {
+ uint8_t opc;
+ uint8_t rsvd1[3];
+ uint32_t dw0;
+ uint32_t dw1;
+ uint32_t mic;
+} NMIRequest;
+
+typedef struct NMIResponse {
+ uint8_t status;
+ uint8_t response[3];
+ uint8_t payload[]; /* includes the Message Integrity Check */
+} NMIResponse;
+
+typedef enum NMIReadDSType {
+ NMI_CMD_READ_NMI_DS_SUBSYSTEM = 0x0,
+ NMI_CMD_READ_NMI_DS_PORTS = 0x1,
+ NMI_CMD_READ_NMI_DS_CTRL_LIST = 0x2,
+ NMI_CMD_READ_NMI_DS_CTRL_INFO = 0x3,
+ NMI_CMD_READ_NMI_DS_CMD_SUPPORT = 0x4,
+ NMI_CMD_READ_NMI_DS_MEB_CMD_SUPPORT = 0x5,
+} NMIReadDSType;
+
+static void nmi_set_parameter_error(NMIDevice *nmi, uint8_t bit, uint16_t byte)
+{
+ nmi->scratch[nmi->pos++] = 0x4;
+ nmi->scratch[nmi->pos++] = bit;
+ nmi->scratch[nmi->pos++] = (byte >> 4) & 0xf;
+ nmi->scratch[nmi->pos++] = byte & 0xf;
+}
+
+static void nmi_set_error(NMIDevice *nmi, uint8_t status)
+{
+ uint8_t buf[4] = {};
+
+ buf[0] = status;
+
+ memcpy(nmi->scratch + nmi->pos, buf, 4);
+ nmi->pos += 4;
+}
+
+static void nmi_handle_mi_read_nmi_ds(NMIDevice *nmi, NMIRequest *request)
+{
+ I2CSlave *i2c = I2C_SLAVE(nmi);
+
+ uint32_t dw0 = le32_to_cpu(request->dw0);
+ uint8_t dtyp = (dw0 >> 24) & 0xf;
+ uint8_t *buf;
+ size_t len;
+
+ trace_nmi_handle_mi_read_nmi_ds(dtyp);
+
+ static uint8_t nmi_ds_subsystem[36] = {
+ 0x00, /* success */
+ 0x20, /* response data length */
+ 0x00, 0x00, /* reserved */
+ 0x00, /* number of ports */
+ 0x01, /* major version */
+ 0x01, /* minor version */
+ };
+
+ static uint8_t nmi_ds_ports[36] = {
+ 0x00, /* success */
+ 0x20, /* response data length */
+ 0x00, 0x00, /* reserved */
+ 0x02, /* port type (smbus) */
+ 0x00, /* reserved */
+ 0x40, 0x00, /* maximum mctp transission unit size (64 bytes) */
+ 0x00, 0x00, 0x00, 0x00, /* management endpoint buffer size */
+ 0x00, 0x00, /* vpd i2c address/freq */
+ 0x00, 0x01, /* management endpoint i2c address/freq */
+ };
+
+ static uint8_t nmi_ds_empty[8] = {
+ 0x00, /* success */
+ 0x02, /* response data length */
+ 0x00, 0x00, /* reserved */
+ 0x00, 0x00, /* number of controllers */
+ 0x00, 0x00, /* padding */
+ };
+
+ switch (dtyp) {
+ case NMI_CMD_READ_NMI_DS_SUBSYSTEM:
+ len = 36;
+ buf = nmi_ds_subsystem;
+
+ break;
+
+ case NMI_CMD_READ_NMI_DS_PORTS:
+ len = 36;
+ buf = nmi_ds_ports;
+
+ /* patch in the i2c address of the endpoint */
+ buf[14] = i2c->address;
+
+ break;
+
+ case NMI_CMD_READ_NMI_DS_CTRL_LIST:
+ case NMI_CMD_READ_NMI_DS_CMD_SUPPORT:
+ case NMI_CMD_READ_NMI_DS_MEB_CMD_SUPPORT:
+ len = 8;
+ buf = nmi_ds_empty;
+
+ break;
+
+ default:
+ nmi_set_parameter_error(nmi, offsetof(NMIRequest, dw0) + 4, 0);
+
+ return;
+ }
+
+ memcpy(nmi->scratch + nmi->pos, buf, len);
+ nmi->pos += len;
+}
+
+enum {
+ NMI_CMD_CONFIGURATION_GET_SMBUS_FREQ = 0x1,
+ NMI_CMD_CONFIGURATION_GET_HEALTH_STATUS_CHANGE = 0x2,
+ NMI_CMD_CONFIGURATION_GET_MCTP_TRANSMISSION_UNIT = 0x3,
+};
+
+static void nmi_handle_mi_config_get(NMIDevice *nmi, NMIRequest *request)
+{
+ uint32_t dw0 = le32_to_cpu(request->dw0);
+ uint8_t identifier = dw0 & 0xff;
+ uint8_t *buf;
+
+ static uint8_t smbus_freq[4] = {
+ 0x00, /* success */
+ 0x01, 0x00, 0x00, /* 100 kHz */
+ };
+
+ static uint8_t mtu[4] = {
+ 0x00, /* success */
+ 0x40, 0x00, 0x00, /* 64 */
+ };
+
+ trace_nmi_handle_mi_config_get(identifier);
+
+ switch (identifier) {
+ case NMI_CMD_CONFIGURATION_GET_SMBUS_FREQ:
+ buf = smbus_freq;
+ break;
+
+ case NMI_CMD_CONFIGURATION_GET_MCTP_TRANSMISSION_UNIT:
+ buf = mtu;
+ break;
+
+ default:
+ nmi_set_parameter_error(nmi, 0x0, offsetof(NMIRequest, dw0));
+ return;
+ }
+
+ memcpy(nmi->scratch + nmi->pos, buf, 4);
+ nmi->pos += 4;
+}
+
+enum {
+ NMI_CMD_READ_NMI_DS = 0x0,
+ NMI_CMD_CONFIGURATION_GET = 0x4,
+};
+
+static void nmi_handle_mi(NMIDevice *nmi, NMIMessage *msg)
+{
+ NMIRequest *request = (NMIRequest *)msg->payload;
+
+ trace_nmi_handle_mi(request->opc);
+
+ switch (request->opc) {
+ case NMI_CMD_READ_NMI_DS:
+ nmi_handle_mi_read_nmi_ds(nmi, request);
+ break;
+
+ case NMI_CMD_CONFIGURATION_GET:
+ nmi_handle_mi_config_get(nmi, request);
+ break;
+
+ default:
+ nmi_set_parameter_error(nmi, 0x0, 0x0);
+ fprintf(stderr, "nmi command 0x%x not handled\n", request->opc);
+
+ break;
+ }
+}
+
+enum {
+ NMI_MESSAGE_TYPE_NMI = 0x1,
+};
+
+static void nmi_handle(MCTPI2CEndpoint *mctp)
+{
+ NMIDevice *nmi = NMI_I2C_DEVICE(mctp);
+ NMIMessage *msg = (NMIMessage *)nmi->buffer;
+ uint32_t crc;
+ uint8_t nmimt;
+
+ uint8_t buf[] = {
+ MCTP_MESSAGE_TYPE_NMI | MCTP_MESSAGE_IC,
+ FIELD_DP8(msg->nmp, NMI_NMP, ROR, 1),
+ 0x0, 0x0,
+ };
+
+ memcpy(nmi->scratch, buf, sizeof(buf));
+ nmi->pos = sizeof(buf);
+
+ nmimt = FIELD_EX8(msg->nmp, NMI_NMP, NMIMT);
+
+ trace_nmi_handle_msg(nmimt);
+
+ switch (nmimt) {
+ case NMI_MESSAGE_TYPE_NMI:
+ nmi_handle_mi(nmi, msg);
+ break;
+
+ default:
+ fprintf(stderr, "nmi message type 0x%x not handled\n", nmimt);
+
+ nmi_set_error(nmi, 0x3);
+
+ break;
+ }
+
+ /* add message integrity check */
+ memset(nmi->scratch + nmi->pos, 0x0, sizeof(crc));
+
+ crc = crc32c(0xffffffff, nmi->scratch, nmi->pos);
+ memcpy(nmi->scratch + nmi->pos, &crc, sizeof(crc));
+
+ nmi->len = nmi->pos + sizeof(crc);
+ nmi->pos = 0;
+
+ i2c_mctp_schedule_send(mctp);
+}
+
+static size_t nmi_get_buf(MCTPI2CEndpoint *mctp, const uint8_t **buf,
+ size_t maxlen, uint8_t *mctp_flags)
+{
+ NMIDevice *nmi = NMI_I2C_DEVICE(mctp);
+ size_t len;
+
+ len = MIN(maxlen, nmi->len - nmi->pos);
+
+ if (len == 0) {
+ return 0;
+ }
+
+ if (nmi->pos == 0) {
+ *mctp_flags |= MCTP_H_FLAGS_SOM;
+ }
+
+ *buf = nmi->scratch + nmi->pos;
+ nmi->pos += len;
+
+ if (nmi->pos == nmi->len) {
+ *mctp_flags |= MCTP_H_FLAGS_EOM;
+
+ nmi->pos = nmi->len = 0;
+ }
+
+ return len;
+}
+
+static int nmi_put_buf(MCTPI2CEndpoint *mctp, uint8_t *buf, size_t len)
+{
+ NMIDevice *nmi = NMI_I2C_DEVICE(mctp);
+
+ if (nmi->len + len > NMI_MAX_MESSAGE_LENGTH) {
+ return -1;
+ }
+
+ memcpy(nmi->buffer + nmi->len, buf, len);
+ nmi->len += len;
+
+ return 0;
+}
+
+static void nmi_reset(MCTPI2CEndpoint *mctp)
+{
+ NMIDevice *nmi = NMI_I2C_DEVICE(mctp);
+ nmi->len = 0;
+}
+
+static size_t nmi_get_types(MCTPI2CEndpoint *mctp, const uint8_t **data)
+{
+ static const uint8_t buf[] = {
+ 0x0, 0x1, MCTP_MESSAGE_TYPE_NMI,
+ };
+
+ *data = buf;
+
+ return sizeof(buf);
+}
+
+static void nvme_mi_class_init(ObjectClass *oc, void *data)
+{
+ MCTPI2CEndpointClass *mc = MCTP_I2C_ENDPOINT_CLASS(oc);
+
+ mc->get_types = nmi_get_types;
+
+ mc->get_buf = nmi_get_buf;
+ mc->put_buf = nmi_put_buf;
+
+ mc->handle = nmi_handle;
+ mc->reset = nmi_reset;
+}
+
+static const TypeInfo nvme_mi = {
+ .name = TYPE_NMI_I2C_DEVICE,
+ .parent = TYPE_MCTP_I2C_ENDPOINT,
+ .instance_size = sizeof(NMIDevice),
+ .class_init = nvme_mi_class_init,
+};
+
+static void register_types(void)
+{
+ type_register_static(&nvme_mi);
+}
+
+type_init(register_types);
diff --git a/hw/nvme/trace-events b/hw/nvme/trace-events
index 9afddf3b951c..e71171c539bd 100644
--- a/hw/nvme/trace-events
+++ b/hw/nvme/trace-events
@@ -215,3 +215,9 @@ pci_nvme_ub_db_wr_invalid_sq(uint32_t qid) "submission queue doorbell write for
pci_nvme_ub_db_wr_invalid_sqtail(uint32_t qid, uint16_t new_tail) "submission queue doorbell write value beyond queue size, sqid=%"PRIu32", new_head=%"PRIu16", ignoring"
pci_nvme_ub_unknown_css_value(void) "unknown value in cc.css field"
pci_nvme_ub_too_many_mappings(void) "too many prp/sgl mappings"
+
+# nmi-i2c
+nmi_handle_mi_read_nmi_ds(uint8_t dtyp) "dtyp 0x%"PRIx8""
+nmi_handle_mi_config_get(uint8_t identifier) "identifier 0x%"PRIx8""
+nmi_handle_mi(uint8_t opc) "opc 0x%"PRIx8""
+nmi_handle_msg(uint8_t nmint) "nmint 0x%"PRIx8""
--
2.40.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v3 3/3] hw/nvme: add nvme management interface model
2023-05-31 11:47 ` [PATCH v3 3/3] hw/nvme: add nvme management interface model Klaus Jensen
@ 2023-05-31 15:39 ` Jonathan Cameron via
0 siblings, 0 replies; 10+ messages in thread
From: Jonathan Cameron via @ 2023-05-31 15:39 UTC (permalink / raw)
To: Klaus Jensen
Cc: qemu-devel, Corey Minyard, Keith Busch, Jason Wang,
Lior Weintraub, Paolo Bonzini, Jeremy Kerr, qemu-arm,
Matt Johnston, Peter Delevoryas, qemu-block,
Cédric Le Goater, Klaus Jensen, Peter Maydell, gost.dev
On Wed, 31 May 2023 13:47:44 +0200
Klaus Jensen <its@irrelevant.dk> wrote:
> From: Klaus Jensen <k.jensen@samsung.com>
>
> Add the 'nmi-i2c' device that emulates an NVMe Management Interface
> controller.
>
> Initial support is very basic (Read NMI DS, Configuration Get).
>
> This is based on previously posted code by Padmakar Kalghatgi, Arun
> Kumar Agasar and Saurav Kumar.
>
> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
A few comments inline - I dug into the specs this time so some
new questions.
Jonathan
> diff --git a/hw/nvme/nmi-i2c.c b/hw/nvme/nmi-i2c.c
> new file mode 100644
> index 000000000000..38e43e48fa51
> --- /dev/null
> +++ b/hw/nvme/nmi-i2c.c
> @@ -0,0 +1,367 @@
> +/*
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + *
> + * SPDX-FileCopyrightText: Copyright (c) 2022 Samsung Electronics Co., Ltd.
Update to 2023?
> +typedef struct NMIRequest {
> + uint8_t opc;
> + uint8_t rsvd1[3];
> + uint32_t dw0;
> + uint32_t dw1;
> + uint32_t mic;
> +} NMIRequest;
> +
> +typedef struct NMIResponse {
> + uint8_t status;
> + uint8_t response[3];
> + uint8_t payload[]; /* includes the Message Integrity Check */
> +} NMIResponse;
Not used.
> +
> +typedef enum NMIReadDSType {
> + NMI_CMD_READ_NMI_DS_SUBSYSTEM = 0x0,
> + NMI_CMD_READ_NMI_DS_PORTS = 0x1,
> + NMI_CMD_READ_NMI_DS_CTRL_LIST = 0x2,
> + NMI_CMD_READ_NMI_DS_CTRL_INFO = 0x3,
> + NMI_CMD_READ_NMI_DS_CMD_SUPPORT = 0x4,
> + NMI_CMD_READ_NMI_DS_MEB_CMD_SUPPORT = 0x5,
> +} NMIReadDSType;
> +
> +static void nmi_set_parameter_error(NMIDevice *nmi, uint8_t bit, uint16_t byte)
> +{
> + nmi->scratch[nmi->pos++] = 0x4;
> + nmi->scratch[nmi->pos++] = bit;
Mask bit to only 3 bits?
> + nmi->scratch[nmi->pos++] = (byte >> 4) & 0xf;
> + nmi->scratch[nmi->pos++] = byte & 0xf;
Not following how byte is split up. Figure 29 in 1.1d suggests it should be
in bits 23:08 and this doesn't match that. Perhaps a reference given I guess
I'm looking at wrong thing.
> +}
> +static void nmi_handle_mi_read_nmi_ds(NMIDevice *nmi, NMIRequest *request)
> +{
> + I2CSlave *i2c = I2C_SLAVE(nmi);
> +
> + uint32_t dw0 = le32_to_cpu(request->dw0);
> + uint8_t dtyp = (dw0 >> 24) & 0xf;
> + uint8_t *buf;
> + size_t len;
> +
> + trace_nmi_handle_mi_read_nmi_ds(dtyp);
> +
> + static uint8_t nmi_ds_subsystem[36] = {
> + 0x00, /* success */
> + 0x20, /* response data length */
Not the easiest datasheet to read, but I think length is 2 bytes.
Figure 93 in the 1.2b NMI spec has it as bits 15:00 in
a 24 bit field. Ah. I see this is 1.1 definition, in that it's
the same but in figure 89.
> + 0x00, 0x00, /* reserved */
> + 0x00, /* number of ports */
> + 0x01, /* major version */
> + 0x01, /* minor version */
> + };
> +
> + static uint8_t nmi_ds_ports[36] = {
> + 0x00, /* success */
> + 0x20, /* response data length */
As above - this is 2 bytes.
> + 0x00, 0x00, /* reserved */
> + 0x02, /* port type (smbus) */
> + 0x00, /* reserved */
> + 0x40, 0x00, /* maximum mctp transission unit size (64 bytes) */
> + 0x00, 0x00, 0x00, 0x00, /* management endpoint buffer size */
> + 0x00, 0x00, /* vpd i2c address/freq */
Give separate bytes for the two things, why not just have two lines and
a comment for each one?
> + 0x00, 0x01, /* management endpoint i2c address/freq */
Same here though second byte isn't anything to do with frequency. Documnted
as NVMe Basic Management and indicates if that command is supported.
> + };
> +
> + static uint8_t nmi_ds_empty[8] = {
> + 0x00, /* success */
> + 0x02, /* response data length */
> + 0x00, 0x00, /* reserved */
> + 0x00, 0x00, /* number of controllers */
A reference for this would be good as I'm not sure it's defined in the NMI spec.
Is it the controller list from 4.4.1 in the main NVME 2.0 spec?
> + 0x00, 0x00, /* padding */
> + };
> +
> + switch (dtyp) {
> + case NMI_CMD_READ_NMI_DS_SUBSYSTEM:
> + len = 36;
sizeof(nmi_ds_subsystem) Might as well keep that 36 in just one place.
> + buf = nmi_ds_subsystem;
> +
> + break;
> +
> + case NMI_CMD_READ_NMI_DS_PORTS:
> + len = 36;
> + buf = nmi_ds_ports;
same here?
> +
> + /* patch in the i2c address of the endpoint */
> + buf[14] = i2c->address;
If you have multiple instances of this as they will
race over the static buffer. Just make it non static and add
a comment on why.
> +
> + break;
> +
> + case NMI_CMD_READ_NMI_DS_CTRL_LIST:
> + case NMI_CMD_READ_NMI_DS_CMD_SUPPORT:
> + case NMI_CMD_READ_NMI_DS_MEB_CMD_SUPPORT:
> + len = 8;
> + buf = nmi_ds_empty;
> +
> + break;
> +
> + default:
> + nmi_set_parameter_error(nmi, offsetof(NMIRequest, dw0) + 4, 0);
> +
> + return;
> + }
> +
> + memcpy(nmi->scratch + nmi->pos, buf, len);
> + nmi->pos += len;
> +}
> +
> +enum {
> + NMI_CMD_CONFIGURATION_GET_SMBUS_FREQ = 0x1,
> + NMI_CMD_CONFIGURATION_GET_HEALTH_STATUS_CHANGE = 0x2,
> + NMI_CMD_CONFIGURATION_GET_MCTP_TRANSMISSION_UNIT = 0x3,
> +};
> +
> +static void nmi_handle_mi_config_get(NMIDevice *nmi, NMIRequest *request)
> +{
> + uint32_t dw0 = le32_to_cpu(request->dw0);
> + uint8_t identifier = dw0 & 0xff;
> + uint8_t *buf;
> +
> + static uint8_t smbus_freq[4] = {
> + 0x00, /* success */
> + 0x01, 0x00, 0x00, /* 100 kHz */
> + };
> +
> + static uint8_t mtu[4] = {
> + 0x00, /* success */
> + 0x40, 0x00, 0x00, /* 64 */
2 bytes only I think with another reserved.
Figure 66 in 1.1d
> + };
> +
> + trace_nmi_handle_mi_config_get(identifier);
> +
> + switch (identifier) {
> + case NMI_CMD_CONFIGURATION_GET_SMBUS_FREQ:
> + buf = smbus_freq;
> + break;
> +
> + case NMI_CMD_CONFIGURATION_GET_MCTP_TRANSMISSION_UNIT:
> + buf = mtu;
> + break;
> +
> + default:
> + nmi_set_parameter_error(nmi, 0x0, offsetof(NMIRequest, dw0));
> + return;
> + }
> +
> + memcpy(nmi->scratch + nmi->pos, buf, 4);
> + nmi->pos += 4;
> +}
> +
> +enum {
> + NMI_CMD_READ_NMI_DS = 0x0,
> + NMI_CMD_CONFIGURATION_GET = 0x4,
> +};
> +
> +static void nmi_handle_mi(NMIDevice *nmi, NMIMessage *msg)
> +{
> + NMIRequest *request = (NMIRequest *)msg->payload;
> +
> + trace_nmi_handle_mi(request->opc);
> +
> + switch (request->opc) {
> + case NMI_CMD_READ_NMI_DS:
> + nmi_handle_mi_read_nmi_ds(nmi, request);
> + break;
> +
> + case NMI_CMD_CONFIGURATION_GET:
> + nmi_handle_mi_config_get(nmi, request);
> + break;
> +
> + default:
> + nmi_set_parameter_error(nmi, 0x0, 0x0);
> + fprintf(stderr, "nmi command 0x%x not handled\n", request->opc);
> +
> + break;
> + }
> +}
> +
> +enum {
> + NMI_MESSAGE_TYPE_NMI = 0x1,
> +};
> +
> +static size_t nmi_get_types(MCTPI2CEndpoint *mctp, const uint8_t **data)
> +{
> + static const uint8_t buf[] = {
> + 0x0, 0x1, MCTP_MESSAGE_TYPE_NMI,
> + };
Perhaps a comment that the 0x1 is the length. Or you could define
a structure for this with a variable length final field?
Also, should the control type be reported? I couldn't find a statement
that it shouldn't and it has a message ID.
> +
> + *data = buf;
> +
> + return sizeof(buf);
> +}
> +
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 0/3] hw/{i2c, nvme}: mctp endpoint, nvme management interface model
2023-05-31 11:47 [PATCH v3 0/3] hw/{i2c, nvme}: mctp endpoint, nvme management interface model Klaus Jensen
` (2 preceding siblings ...)
2023-05-31 11:47 ` [PATCH v3 3/3] hw/nvme: add nvme management interface model Klaus Jensen
@ 2023-06-01 19:42 ` Corey Minyard
3 siblings, 0 replies; 10+ messages in thread
From: Corey Minyard @ 2023-06-01 19:42 UTC (permalink / raw)
To: Klaus Jensen
Cc: qemu-devel, Corey Minyard, Keith Busch, Jason Wang,
Lior Weintraub, Paolo Bonzini, Jeremy Kerr, qemu-arm,
Matt Johnston, Peter Delevoryas, Jonathan Cameron, qemu-block,
Cédric Le Goater, Klaus Jensen, Peter Maydell, gost.dev
On Wed, May 31, 2023 at 01:47:41PM +0200, Klaus Jensen wrote:
> From: Klaus Jensen <k.jensen@samsung.com>
>
> This adds a generic MCTP endpoint model that other devices may derive
> from. I'm not 100% happy with the design of the class methods, but it's
> a start.
>
> Also included is a very basic implementation of an NVMe-MI device,
> supporting only a small subset of the required commands. Lior (CC'ed) has some
> patches coming up that adds futher support.
>
> Since this all relies on i2c target mode, this can currently only be
> used with an SoC that includes the Aspeed I2C controller.
>
> The easiest way to get up and running with this, is to grab my buildroot
> overlay[1]. It includes modified a modified dts as well as a couple of
> required packages.
>
> QEMU can then be launched along these lines:
>
> qemu-system-arm \
> -nographic \
> -M ast2600-evb \
> -kernel output/images/zImage \
> -initrd output/images/rootfs.cpio \
> -dtb output/images/aspeed-ast2600-evb-nmi.dtb \
> -nic user,hostfwd=tcp::2222-:22 \
> -device nmi-i2c,address=0x3a \
> -serial mon:stdio
>
> From within the booted system,
>
> mctp addr add 8 dev mctpi2c15
> mctp link set mctpi2c15 up
> mctp route add 9 via mctpi2c15
> mctp neigh add 9 dev mctpi2c15 lladdr 0x3a
> mi-mctp 1 9 info
>
> Comments are very welcome!
>
> [1]: https://github.com/birkelund/buildroots/tree/main/mctp-i2c
>
> Changes since v2
> ~~~~~~~~~~~~~~~~
>
> - Applied a bunch of feedback from Jonathan:
> + Moved a lot of internally used structs out of the include headers
> and into the source files.
> + Added spec references in various places
> + Split the patch for i2c_smbus_pec() into its own
> + Fix a compile error (and bug) in nmi-i2c.c.
>
> - From Corey:
> + Reworked the buffer handling. The deriving devices now returns a
> pointer to their own buffer that the mctp core copies into.
You didn't do what I asked here, I guess I wasn't clear. You have:
+static void i2c_mctp_handle_control_set_eid(MCTPI2CEndpoint *mctp, uint8_t eid)
+{
+ mctp->my_eid = eid;
+
+ uint8_t buf[] = {
+ 0x0, 0x0, eid, 0x0,
+ };
+
+ memcpy(i2c_mctp_control_data(mctp->buffer), buf, sizeof(buf));
+ mctp->len += sizeof(buf);
+}
That style of programming can lead to buffer overruns as code changes,
as you aren't checking the length of the target buffer. I don't think
there are any issues now, but as people change the code you might end up
with one if someone gets a length wrong.
What I would like is for you to create a function like:
i2c_mctp_add_bytes(mctp, buf, len)
that checks that len bytes will fit, then does the addition of the
bytes. You need to adjust this to fit how you are doing things, and you
probably want one that adds just one byte, but hopefully you get the idea.
I'm sorry to be picky, but I've seen and fixed too many buffer overruns
(including one in the qemu i2c code) in situations like this. Corey's
rule is: Never add anything to a buffer without checking the length.
Everything else looks good.
-corey
> + Added a couple of extra debugging trace events.
>
> Changes since v1
> ~~~~~~~~~~~~~~~~
>
> - Fix SPDX-License tag for hw/nvme/nmi-i2c.c (Philippe)
> - Add some asserts to verify buffer indices (by request from Corey).
> - Drop short packets that could result in underflow (Corey)
> - Move i2c_smbus_pec() to smbus common code (Corey)
> - A couple of logic fixes (patch from Jeremy squashed in)
> - Added a patch to handle messages with dest eid 0 (Matt)
> Maybe squash this as well.
>
> Klaus Jensen (3):
> hw/i2c: add smbus pec utility function
> hw/i2c: add mctp core
> hw/nvme: add nvme management interface model
>
> MAINTAINERS | 7 +
> hw/arm/Kconfig | 1 +
> hw/i2c/Kconfig | 4 +
> hw/i2c/mctp.c | 398 ++++++++++++++++++++++++++++++++++
> hw/i2c/meson.build | 1 +
> hw/i2c/smbus_master.c | 28 +++
> hw/i2c/trace-events | 13 ++
> hw/nvme/meson.build | 1 +
> hw/nvme/nmi-i2c.c | 367 +++++++++++++++++++++++++++++++
> hw/nvme/trace-events | 6 +
> include/hw/i2c/mctp.h | 137 ++++++++++++
> include/hw/i2c/smbus_master.h | 2 +
> include/net/mctp.h | 28 +++
> 13 files changed, 993 insertions(+)
> create mode 100644 hw/i2c/mctp.c
> create mode 100644 hw/nvme/nmi-i2c.c
> create mode 100644 include/hw/i2c/mctp.h
> create mode 100644 include/net/mctp.h
>
> --
> 2.40.0
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread