From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-ppc@nongnu.org
Cc: "Nicholas Piggin" <npiggin@gmail.com>,
qemu-devel@nongnu.org,
"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
"Cédric Le Goater" <clg@kaod.org>
Subject: [PATCH 0/4] ppc/pnv: Add chiptod and core timebase state machine models
Date: Sun, 4 Jun 2023 09:36:08 +1000 [thread overview]
Message-ID: <20230603233612.125879-1-npiggin@gmail.com> (raw)
This adds support for chiptod and core timebase state machine models in
the powernv POWER9 and POWER10 models.
This does not actually change the time or the value in TB registers
(because they are alrady synced in QEMU), but it does go through the
motions. It is enough to be able to run skiboot's chiptod initialisation
code that synchronises core timebases (after a patch to prevent skiboot
skipping chiptod for QEMU, posted to skiboot mailing list).
Sorry there was some delay since the last posting. There is a bit more
interest in this recently but feedback and comments from RFC was not
forgotten and is much appreciated.
https://lists.gnu.org/archive/html/qemu-ppc/2022-08/msg00324.html
I think I accounted for everything except moving register defines to the
.h file. I'm on the fence about that but if they are only used in the .c
file I think it's okay to keep them there for now. I cut out a lot of
unused ones so it's not so cluttered now.
Lots of other changes and fixes since that RFC. Notably:
- Register names changed to match the workbook names instead of skiboot.
- TFMR moved to timebase_helper.c from misc_helper.c
- More comprehensive model and error checking, particularly of TFMR.
- POWER10 with multi-chip support.
- chiptod and core timebase linked via specific state instead of TFMR.
There is still a vast amount that is not modeled, but most of it related
to error handling, injection, failover, etc that is very complicated and
not required for normal operation.
Thanks,
Nick
Nicholas Piggin (4):
pnv/chiptod: Add POWER9/10 chiptod model
target/ppc: Tidy POWER book4 SPR registration
target/ppc: add TFMR SPR implementation with read and write helpers
target/ppc: Implement core timebase state machine and TFMR
hw/ppc/meson.build | 1 +
hw/ppc/pnv.c | 38 +++
hw/ppc/pnv_chiptod.c | 488 +++++++++++++++++++++++++++++++++++
hw/ppc/pnv_xscom.c | 2 +
hw/ppc/trace-events | 4 +
include/hw/ppc/pnv_chip.h | 3 +
include/hw/ppc/pnv_chiptod.h | 64 +++++
include/hw/ppc/pnv_core.h | 3 +
include/hw/ppc/pnv_xscom.h | 9 +
target/ppc/cpu.h | 40 +++
target/ppc/cpu_init.c | 92 ++++---
target/ppc/helper.h | 2 +
target/ppc/spr_common.h | 2 +
target/ppc/timebase_helper.c | 156 +++++++++++
target/ppc/translate.c | 10 +
15 files changed, 882 insertions(+), 32 deletions(-)
create mode 100644 hw/ppc/pnv_chiptod.c
create mode 100644 include/hw/ppc/pnv_chiptod.h
--
2.40.1
next reply other threads:[~2023-06-03 23:36 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-03 23:36 Nicholas Piggin [this message]
2023-06-03 23:36 ` [PATCH 1/4] pnv/chiptod: Add POWER9/10 chiptod model Nicholas Piggin
2023-06-05 14:57 ` Cédric Le Goater
2023-06-14 5:30 ` Nicholas Piggin
2023-06-14 7:01 ` Cédric Le Goater
2023-06-03 23:36 ` [PATCH 2/4] target/ppc: Tidy POWER book4 SPR registration Nicholas Piggin
2023-06-05 14:58 ` Cédric Le Goater
2023-06-03 23:36 ` [PATCH 3/4] target/ppc: add TFMR SPR implementation with read and write helpers Nicholas Piggin
2023-06-14 8:38 ` Cédric Le Goater
2023-06-03 23:36 ` [PATCH 4/4] target/ppc: Implement core timebase state machine and TFMR Nicholas Piggin
2023-06-14 8:55 ` Cédric Le Goater
2023-06-06 13:59 ` [PATCH 0/4] ppc/pnv: Add chiptod and core timebase state machine models Cédric Le Goater
2023-06-14 5:14 ` Nicholas Piggin
2023-06-14 8:54 ` Cédric Le Goater
2023-06-15 2:18 ` Nicholas Piggin
2023-06-15 9:45 ` Cédric Le Goater
2023-06-22 7:30 ` Cédric Le Goater
2023-06-22 9:54 ` Nicholas Piggin
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