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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id m12-20020adfe0cc000000b003078681a1e8sm1056052wri.54.2023.06.08.02.43.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jun 2023 02:43:41 -0700 (PDT) Date: Thu, 8 Jun 2023 11:43:34 +0200 From: Andrew Jones To: Tommy Wu Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, frank.chang@sifive.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, richard.henderson@linaro.org Subject: Re: [PATCH v4 0/4] target/riscv: Add Smrnmi support. Message-ID: <20230608-01a21738d16a20808eceb795@orel> References: <20230608072314.3561109-1-tommy.wu@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230608072314.3561109-1-tommy.wu@sifive.com> Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=ajones@ventanamicro.com; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Jun 08, 2023 at 12:23:10AM -0700, Tommy Wu wrote: > This patchset added support for Smrnmi Extension in RISC-V. > > There are four new CSRs and one new instruction added to allow NMI to be > resumable in RISC-V, which are: > > ============================================================= > * mnscratch (0x740) > * mnepc (0x741) > * mncause (0x742) > * mnstatus (0x744) > ============================================================= > * mnret: To return from RNMI interrupt/exception handler. > ============================================================= > > RNMI also has higher priority than any other interrupts or exceptions > and cannot be disabled by software. > > RNMI may be used to route to other devices such as Bus Error Unit or > Watchdog Timer in the future. > > The interrupt/exception trap handler addresses of RNMI are > implementation defined. Is there an M-mode software PoC for this with implemented handlers? Thanks, drew > > Changelog: > > v4 > * Fix some coding style issues. > ( Thank Daniel for the suggestions. ) > > v3 > * Update to the newest version of Smrnmi extension specification. > > v2 > * split up the series into more commits for convenience of review. > * add missing rnmi_irqvec and rnmi_excpvec properties to riscv_harts. > > Tommy Wu (4): > target/riscv: Add Smrnmi cpu extension. > target/riscv: Add Smrnmi CSRs. > target/riscv: Handle Smrnmi interrupt and exception. > target/riscv: Add Smrnmi mnret instruction. > > hw/riscv/riscv_hart.c | 21 +++++ > include/hw/riscv/riscv_hart.h | 4 + > target/riscv/cpu.c | 18 ++++ > target/riscv/cpu.h | 11 +++ > target/riscv/cpu_bits.h | 23 ++++++ > target/riscv/cpu_helper.c | 81 ++++++++++++++++-- > target/riscv/csr.c | 82 +++++++++++++++++++ > target/riscv/helper.h | 1 + > target/riscv/insn32.decode | 3 + > .../riscv/insn_trans/trans_privileged.c.inc | 12 +++ > target/riscv/op_helper.c | 49 +++++++++++ > 11 files changed, 300 insertions(+), 5 deletions(-) > > -- > 2.31.1 > >