[PATCH] target/riscv/vector_helper.c: clean up reference of MTYPE

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* [PATCH] target/riscv/vector_helper.c: clean up reference of MTYPE
@ 2023-06-08  5:35 Xiao Wang
  2023-06-09 17:57 ` Daniel Henrique Barboza
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Xiao Wang @ 2023-06-08  5:35 UTC (permalink / raw)
  To: qemu-devel
  Cc: Xiao Wang, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
	Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs

There's no code using MTYPE, which was a concept used in older vector
implementation.

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
---
 target/riscv/vector_helper.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index f261e726c2..1e06e7447c 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -378,7 +378,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
 
 /*
  * masked unit-stride load and store operation will be a special case of
- * stride, stride = NF * sizeof (MTYPE)
+ * stride, stride = NF * sizeof (ETYPE)
  */
 
 #define GEN_VEXT_LD_US(NAME, ETYPE, LOAD_FN)                            \
@@ -650,10 +650,6 @@ GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d)
 #define DO_MAX(N, M)  ((N) >= (M) ? (N) : (M))
 #define DO_MIN(N, M)  ((N) >= (M) ? (M) : (N))
 
-/* Unsigned min/max */
-#define DO_MAXU(N, M) DO_MAX((UMTYPE)N, (UMTYPE)M)
-#define DO_MINU(N, M) DO_MIN((UMTYPE)N, (UMTYPE)M)
-
 /*
  * load and store whole register instructions
  */
-- 
2.25.1



^ permalink raw reply related	[flat|nested] 4+ messages in thread

* Re: [PATCH] target/riscv/vector_helper.c: clean up reference of MTYPE
  2023-06-08  5:35 [PATCH] target/riscv/vector_helper.c: clean up reference of MTYPE Xiao Wang
@ 2023-06-09 17:57 ` Daniel Henrique Barboza
  2023-06-12  2:23 ` Alistair Francis
  2023-06-12  2:26 ` LIU Zhiwei
  2 siblings, 0 replies; 4+ messages in thread
From: Daniel Henrique Barboza @ 2023-06-09 17:57 UTC (permalink / raw)
  To: Xiao Wang, qemu-devel
  Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li, Liu Zhiwei,
	open list:RISC-V TCG CPUs



On 6/8/23 02:35, Xiao Wang wrote:
> There's no code using MTYPE, which was a concept used in older vector
> implementation.
> 
> Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/vector_helper.c | 6 +-----
>   1 file changed, 1 insertion(+), 5 deletions(-)
> 
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index f261e726c2..1e06e7447c 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -378,7 +378,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
>   
>   /*
>    * masked unit-stride load and store operation will be a special case of
> - * stride, stride = NF * sizeof (MTYPE)
> + * stride, stride = NF * sizeof (ETYPE)
>    */
>   
>   #define GEN_VEXT_LD_US(NAME, ETYPE, LOAD_FN)                            \
> @@ -650,10 +650,6 @@ GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d)
>   #define DO_MAX(N, M)  ((N) >= (M) ? (N) : (M))
>   #define DO_MIN(N, M)  ((N) >= (M) ? (M) : (N))
>   
> -/* Unsigned min/max */
> -#define DO_MAXU(N, M) DO_MAX((UMTYPE)N, (UMTYPE)M)
> -#define DO_MINU(N, M) DO_MIN((UMTYPE)N, (UMTYPE)M)
> -
>   /*
>    * load and store whole register instructions
>    */


^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH] target/riscv/vector_helper.c: clean up reference of MTYPE
  2023-06-08  5:35 [PATCH] target/riscv/vector_helper.c: clean up reference of MTYPE Xiao Wang
  2023-06-09 17:57 ` Daniel Henrique Barboza
@ 2023-06-12  2:23 ` Alistair Francis
  2023-06-12  2:26 ` LIU Zhiwei
  2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2023-06-12  2:23 UTC (permalink / raw)
  To: Xiao Wang
  Cc: qemu-devel, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
	Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs

On Thu, Jun 8, 2023 at 3:32 PM Xiao Wang <xiao.w.wang@intel.com> wrote:
>
> There's no code using MTYPE, which was a concept used in older vector
> implementation.
>
> Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>  target/riscv/vector_helper.c | 6 +-----
>  1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index f261e726c2..1e06e7447c 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -378,7 +378,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
>
>  /*
>   * masked unit-stride load and store operation will be a special case of
> - * stride, stride = NF * sizeof (MTYPE)
> + * stride, stride = NF * sizeof (ETYPE)
>   */
>
>  #define GEN_VEXT_LD_US(NAME, ETYPE, LOAD_FN)                            \
> @@ -650,10 +650,6 @@ GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d)
>  #define DO_MAX(N, M)  ((N) >= (M) ? (N) : (M))
>  #define DO_MIN(N, M)  ((N) >= (M) ? (M) : (N))
>
> -/* Unsigned min/max */
> -#define DO_MAXU(N, M) DO_MAX((UMTYPE)N, (UMTYPE)M)
> -#define DO_MINU(N, M) DO_MIN((UMTYPE)N, (UMTYPE)M)
> -
>  /*
>   * load and store whole register instructions
>   */
> --
> 2.25.1
>
>


^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH] target/riscv/vector_helper.c: clean up reference of MTYPE
  2023-06-08  5:35 [PATCH] target/riscv/vector_helper.c: clean up reference of MTYPE Xiao Wang
  2023-06-09 17:57 ` Daniel Henrique Barboza
  2023-06-12  2:23 ` Alistair Francis
@ 2023-06-12  2:26 ` LIU Zhiwei
  2 siblings, 0 replies; 4+ messages in thread
From: LIU Zhiwei @ 2023-06-12  2:26 UTC (permalink / raw)
  To: Xiao Wang, qemu-devel
  Cc: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
	Daniel Henrique Barboza, open list:RISC-V TCG CPUs


On 2023/6/8 13:35, Xiao Wang wrote:
> There's no code using MTYPE,
Yes, it means memory access type.
> which was a concept used in older vector
> implementation.
>
> Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
> ---
>   target/riscv/vector_helper.c | 6 +-----
>   1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index f261e726c2..1e06e7447c 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -378,7 +378,7 @@ vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc,
>   
>   /*
>    * masked unit-stride load and store operation will be a special case of
> - * stride, stride = NF * sizeof (MTYPE)
> + * stride, stride = NF * sizeof (ETYPE)
>    */
>   
>   #define GEN_VEXT_LD_US(NAME, ETYPE, LOAD_FN)                            \
> @@ -650,10 +650,6 @@ GEN_VEXT_LDFF(vle64ff_v, int64_t, lde_d)
>   #define DO_MAX(N, M)  ((N) >= (M) ? (N) : (M))
>   #define DO_MIN(N, M)  ((N) >= (M) ? (M) : (N))
>   
> -/* Unsigned min/max */
> -#define DO_MAXU(N, M) DO_MAX((UMTYPE)N, (UMTYPE)M)
> -#define DO_MINU(N, M) DO_MIN((UMTYPE)N, (UMTYPE)M)

This once has been used by the vector atomic instructions, which has 
been moved to the Zvamo.

Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Zhiwei

> -
>   /*
>    * load and store whole register instructions
>    */


^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2023-06-12  2:27 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2023-06-08  5:35 [PATCH] target/riscv/vector_helper.c: clean up reference of MTYPE Xiao Wang
2023-06-09 17:57 ` Daniel Henrique Barboza
2023-06-12  2:23 ` Alistair Francis
2023-06-12  2:26 ` LIU Zhiwei

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