From: Siarhei Volkau <lis8215@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Stefan Markovic" <smarkovic@wavecomp.com>,
"Aleksandar Markovic" <amarkovic@wavecomp.com>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Siarhei Volkau" <lis8215@gmail.com>
Subject: [PATCH 26/33] target/mips: Add emulation of MXU Q16SLL Q16SLR Q16SAR instructions
Date: Thu, 8 Jun 2023 13:42:15 +0300 [thread overview]
Message-ID: <20230608104222.1520143-27-lis8215@gmail.com> (raw)
In-Reply-To: <20230608104222.1520143-1-lis8215@gmail.com>
These instructions are same data shift in various directions, thus one
generation function is implemented for all three.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
---
target/mips/tcg/mxu_translate.c | 78 +++++++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c
index 93644d74e2..418c02eb8e 100644
--- a/target/mips/tcg/mxu_translate.c
+++ b/target/mips/tcg/mxu_translate.c
@@ -400,6 +400,9 @@ enum {
OPC_MXU_D32SLR = 0x31,
OPC_MXU_D32SARL = 0x32,
OPC_MXU_D32SAR = 0x33,
+ OPC_MXU_Q16SLL = 0x34,
+ OPC_MXU_Q16SLR = 0x35,
+ OPC_MXU_Q16SAR = 0x37,
OPC_MXU__POOL19 = 0x38,
};
@@ -1791,6 +1794,72 @@ static void gen_mxu_d32sarl(DisasContext *ctx, bool sarw)
}
}
+/*
+ * Q16SLL XRa, XRd, XRb, XRc, SFT4
+ * Quad 16-bit shift left from XRb and XRc to SFT4
+ * bits (0..15). Store to XRa and XRd respectively.
+ * Q16SLR XRa, XRd, XRb, XRc, SFT4
+ * Quad 16-bit shift logic right from XRb and XRc
+ * to SFT4 bits (0..15). Store to XRa and XRd respectively.
+ * Q16SAR XRa, XRd, XRb, XRc, SFT4
+ * Quad 16-bit shift arithmetic right from XRb and XRc
+ * to SFT4 bits (0..15). Store to XRa and XRd respectively.
+ */
+static void gen_mxu_q16sxx(DisasContext *ctx, bool right, bool arithmetic)
+{
+ uint32_t XRa, XRb, XRc, XRd, sft4;
+
+ XRa = extract32(ctx->opcode, 6, 4);
+ XRb = extract32(ctx->opcode, 10, 4);
+ XRc = extract32(ctx->opcode, 14, 4);
+ XRd = extract32(ctx->opcode, 18, 4);
+ sft4 = extract32(ctx->opcode, 22, 4);
+
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_temp_new();
+ TCGv t3 = tcg_temp_new();
+
+ gen_load_mxu_gpr(t0, XRb);
+ gen_load_mxu_gpr(t2, XRc);
+
+ if (arithmetic) {
+ tcg_gen_sextract_tl(t1, t0, 16, 16);
+ tcg_gen_sextract_tl(t0, t0, 0, 16);
+ tcg_gen_sextract_tl(t3, t2, 16, 16);
+ tcg_gen_sextract_tl(t2, t2, 0, 16);
+ } else {
+ tcg_gen_extract_tl(t1, t0, 16, 16);
+ tcg_gen_extract_tl(t0, t0, 0, 16);
+ tcg_gen_extract_tl(t3, t2, 16, 16);
+ tcg_gen_extract_tl(t2, t2, 0, 16);
+ }
+
+ if (right) {
+ if (arithmetic) {
+ tcg_gen_sari_tl(t0, t0, sft4);
+ tcg_gen_sari_tl(t1, t1, sft4);
+ tcg_gen_sari_tl(t2, t2, sft4);
+ tcg_gen_sari_tl(t3, t3, sft4);
+ } else {
+ tcg_gen_shri_tl(t0, t0, sft4);
+ tcg_gen_shri_tl(t1, t1, sft4);
+ tcg_gen_shri_tl(t2, t2, sft4);
+ tcg_gen_shri_tl(t3, t3, sft4);
+ }
+ } else {
+ tcg_gen_shli_tl(t0, t0, sft4);
+ tcg_gen_shli_tl(t1, t1, sft4);
+ tcg_gen_shli_tl(t2, t2, sft4);
+ tcg_gen_shli_tl(t3, t3, sft4);
+ }
+ tcg_gen_deposit_tl(t0, t0, t1, 16, 16);
+ tcg_gen_deposit_tl(t2, t2, t3, 16, 16);
+
+ gen_store_mxu_gpr(t0, XRa);
+ gen_store_mxu_gpr(t2, XRd);
+}
+
/*
* MXU instruction category max/min/avg
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -4330,6 +4399,15 @@ bool decode_ase_mxu(DisasContext *ctx, uint32_t insn)
case OPC_MXU_D32SAR:
gen_mxu_d32sxx(ctx, true, true);
break;
+ case OPC_MXU_Q16SLL:
+ gen_mxu_q16sxx(ctx, false, false);
+ break;
+ case OPC_MXU_Q16SLR:
+ gen_mxu_q16sxx(ctx, true, false);
+ break;
+ case OPC_MXU_Q16SAR:
+ gen_mxu_q16sxx(ctx, true, true);
+ break;
case OPC_MXU__POOL19:
decode_opc_mxu__pool19(ctx);
break;
--
2.40.0
next prev parent reply other threads:[~2023-06-08 13:21 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-08 10:41 [PATCH 00/33] target/mips: Finalise the Ingenic MXU ASE support Siarhei Volkau
2023-06-08 10:41 ` [PATCH 01/33] target/mips: Add emulation of MXU instructions for 32-bit load/store Siarhei Volkau
2023-06-08 10:41 ` [PATCH 02/33] Add support of two XBurst CPUs Siarhei Volkau
2023-06-08 10:41 ` [PATCH 03/33] target/mips: Add emulation of LXW LXB LXH LXBU LXHU instructions Siarhei Volkau
2023-06-08 10:41 ` [PATCH 04/33] target/mips: Add emulation of S32MADD/MADDU/MSUB/MSUBU instructions Siarhei Volkau
2023-06-08 10:41 ` [PATCH 05/33] target/mips: Add emulation of Q8SLT Q8SLTU instructions Siarhei Volkau
2023-06-08 10:41 ` [PATCH 06/33] target/mips: fix MXU D16MAX D16MIN Q8MAX Q8MIN instructions Siarhei Volkau
2023-06-08 10:41 ` [PATCH 07/33] target/mips: Add emulation of MXU S32SLT D16SLT D16AVG[R] Q8AVG[R] insns Siarhei Volkau
2023-06-08 10:41 ` [PATCH 08/33] target/mips: Add emulation of Q8ADD instruction Siarhei Volkau
2023-06-08 10:41 ` [PATCH 09/33] target/mips: Add emulation of MXU S32CPS D16CPS Q8ABD Q16SAT insns Siarhei Volkau
2023-06-08 10:41 ` [PATCH 10/33] target/mips: Add emulation of MXU D16MULF D16MULE instructions Siarhei Volkau
2023-06-08 10:42 ` [PATCH 11/33] target/mips: Add emulation of MXU D16MACF D16MACE instructions Siarhei Volkau
2023-06-08 10:42 ` [PATCH 12/33] target/mips: Add emulation of MXU D16MADL instruction Siarhei Volkau
2023-06-08 10:42 ` [PATCH 13/33] target/mips: Add emulation of MXU S16MAD instruction Siarhei Volkau
2023-06-08 10:42 ` [PATCH 14/33] target/mips: Add emulation of MXU Q16ADD instruction Siarhei Volkau
2023-06-08 10:42 ` [PATCH 15/33] target/mips: Add emulation of MXU D32ADD instruction Siarhei Volkau
2023-06-08 10:42 ` [PATCH 16/33] target/mips: Add emulation of MXU D32ACC D32ACCM D32ASUM instructions Siarhei Volkau
2023-06-08 10:42 ` [PATCH 17/33] target/mips: Add emulation of MXU D32ADDC instruction Siarhei Volkau
2023-06-08 10:42 ` [PATCH 18/33] target/mips: Add emulation of MXU Q16ACC Q16ACCM D16ASUM instructions Siarhei Volkau
2023-06-08 10:42 ` [PATCH 19/33] target/mips: Add emulation of MXU Q8ADDE Q8ACCE D8SUM D8SUMC instructions Siarhei Volkau
2023-06-08 10:42 ` [PATCH 20/33] target/mips: Add emulation of MXU S8STD S8LDI S8SDI instructions Siarhei Volkau
2023-06-08 10:42 ` [PATCH 21/33] target/mips: Add emulation of MXU S16LDD S16STD S16LDI S16SDI instructions Siarhei Volkau
2023-06-08 10:42 ` [PATCH 22/33] target/mips: Add emulation of MXU S32MUL S32MULU S32EXTR S32EXTRV insns Siarhei Volkau
2023-06-08 10:42 ` [PATCH 23/33] target/mips: Add emulation of MXU S32ALN S32LUI insns Siarhei Volkau
2023-06-08 10:42 ` [PATCH 24/33] target/mips: Add emulation of MXU D32SARL D32SARW instructions Siarhei Volkau
2023-06-08 10:42 ` [PATCH 25/33] target/mips: Add emulation of MXU D32SLL D32SLR D32SAR instructions Siarhei Volkau
2023-06-08 10:42 ` Siarhei Volkau [this message]
2023-06-08 10:42 ` [PATCH 27/33] target/mips: Add emulation of MXU D32/Q16- SLLV/SLRV/SARV instructions Siarhei Volkau
2023-06-08 10:42 ` [PATCH 28/33] target/mips: Add emulation of MXU S32/D16/Q8- MOVZ/MOVN instructions Siarhei Volkau
2023-06-08 10:42 ` [PATCH 29/33] target/mips: Add emulation of MXU Q8MAC Q8MACSU instructions Siarhei Volkau
2023-06-08 10:42 ` [PATCH 30/33] target/mips: Add emulation of MXU Q16SCOP instruction Siarhei Volkau
2023-06-08 10:42 ` [PATCH 31/33] target/mips: Add emulation of MXU Q8MADL instruction Siarhei Volkau
2023-06-08 10:42 ` [PATCH 32/33] target/mips: Add emulation of MXU S32SFL instruction Siarhei Volkau
2023-06-08 10:42 ` [PATCH 33/33] target/mips: Add emulation of MXU Q8SAD instruction Siarhei Volkau
2023-07-10 19:28 ` [PATCH 00/33] target/mips: Finalise the Ingenic MXU ASE support Philippe Mathieu-Daudé
2023-07-20 16:12 ` Siarhei Volkau
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