From: Siarhei Volkau <lis8215@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Stefan Markovic" <smarkovic@wavecomp.com>,
"Aleksandar Markovic" <amarkovic@wavecomp.com>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Siarhei Volkau" <lis8215@gmail.com>
Subject: [PATCH 02/33] Add support of two XBurst CPUs
Date: Thu, 8 Jun 2023 13:41:51 +0300 [thread overview]
Message-ID: <20230608104222.1520143-3-lis8215@gmail.com> (raw)
In-Reply-To: <20230608104222.1520143-1-lis8215@gmail.com>
XBurstR1 - is the MIPS32R1 CPU which aims to cover all Ingenic SoCs
older than JZ4770 and some newer.
XBurstR2 - is the MIPS32R2 CPU which aims to cover all Ingenic SoCs
starting from to JZ4770.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
---
target/mips/cpu-defs.c.inc | 46 ++++++++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index d45f245a67..b67ccf171d 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -117,6 +117,26 @@ const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS32R1,
.mmu_type = MMU_TYPE_R4000,
},
+ {
+ .name = "XBurstR1",
+ .CP0_PRid = 0x1ed0024f,
+ .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (0 << CP0C1_CA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x1278FF17,
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32R1 | ASE_MXU,
+ .mmu_type = MMU_TYPE_R4000,
+ },
{
.name = "4KEmR1",
.CP0_PRid = 0x00018500,
@@ -323,6 +343,32 @@ const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSP_R2,
.mmu_type = MMU_TYPE_R4000,
},
+ {
+ .name = "XBurstR2",
+ .CP0_PRid = 0x2ed1024f,
+ .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
+ (MMU_TYPE_R4000 << CP0C0_MT),
+ .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
+ (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
+ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
+ (1 << CP0C1_CA),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
+ (1 << CP0C3_VInt),
+ .CP0_LLAddr_rw_bitmask = 0,
+ .CP0_LLAddr_shift = 4,
+ .SYNCI_Step = 32,
+ .CCRes = 2,
+ .CP0_Status_rw_bitmask = 0x3778FF1F,
+ .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
+ (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
+ .CP1_fcr31 = 0,
+ .CP1_fcr31_rw_bitmask = 0xFF83FFFF,
+ .SEGBITS = 32,
+ .PABITS = 32,
+ .insn_flags = CPU_MIPS32R2 | ASE_MXU,
+ .mmu_type = MMU_TYPE_R4000,
+ },
{
.name = "M14K",
.CP0_PRid = 0x00019b00,
--
2.40.0
next prev parent reply other threads:[~2023-06-08 13:20 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-08 10:41 [PATCH 00/33] target/mips: Finalise the Ingenic MXU ASE support Siarhei Volkau
2023-06-08 10:41 ` [PATCH 01/33] target/mips: Add emulation of MXU instructions for 32-bit load/store Siarhei Volkau
2023-06-08 10:41 ` Siarhei Volkau [this message]
2023-06-08 10:41 ` [PATCH 03/33] target/mips: Add emulation of LXW LXB LXH LXBU LXHU instructions Siarhei Volkau
2023-06-08 10:41 ` [PATCH 04/33] target/mips: Add emulation of S32MADD/MADDU/MSUB/MSUBU instructions Siarhei Volkau
2023-06-08 10:41 ` [PATCH 05/33] target/mips: Add emulation of Q8SLT Q8SLTU instructions Siarhei Volkau
2023-06-08 10:41 ` [PATCH 06/33] target/mips: fix MXU D16MAX D16MIN Q8MAX Q8MIN instructions Siarhei Volkau
2023-06-08 10:41 ` [PATCH 07/33] target/mips: Add emulation of MXU S32SLT D16SLT D16AVG[R] Q8AVG[R] insns Siarhei Volkau
2023-06-08 10:41 ` [PATCH 08/33] target/mips: Add emulation of Q8ADD instruction Siarhei Volkau
2023-06-08 10:41 ` [PATCH 09/33] target/mips: Add emulation of MXU S32CPS D16CPS Q8ABD Q16SAT insns Siarhei Volkau
2023-06-08 10:41 ` [PATCH 10/33] target/mips: Add emulation of MXU D16MULF D16MULE instructions Siarhei Volkau
2023-06-08 10:42 ` [PATCH 11/33] target/mips: Add emulation of MXU D16MACF D16MACE instructions Siarhei Volkau
2023-06-08 10:42 ` [PATCH 12/33] target/mips: Add emulation of MXU D16MADL instruction Siarhei Volkau
2023-06-08 10:42 ` [PATCH 13/33] target/mips: Add emulation of MXU S16MAD instruction Siarhei Volkau
2023-06-08 10:42 ` [PATCH 14/33] target/mips: Add emulation of MXU Q16ADD instruction Siarhei Volkau
2023-06-08 10:42 ` [PATCH 15/33] target/mips: Add emulation of MXU D32ADD instruction Siarhei Volkau
2023-06-08 10:42 ` [PATCH 16/33] target/mips: Add emulation of MXU D32ACC D32ACCM D32ASUM instructions Siarhei Volkau
2023-06-08 10:42 ` [PATCH 17/33] target/mips: Add emulation of MXU D32ADDC instruction Siarhei Volkau
2023-06-08 10:42 ` [PATCH 18/33] target/mips: Add emulation of MXU Q16ACC Q16ACCM D16ASUM instructions Siarhei Volkau
2023-06-08 10:42 ` [PATCH 19/33] target/mips: Add emulation of MXU Q8ADDE Q8ACCE D8SUM D8SUMC instructions Siarhei Volkau
2023-06-08 10:42 ` [PATCH 20/33] target/mips: Add emulation of MXU S8STD S8LDI S8SDI instructions Siarhei Volkau
2023-06-08 10:42 ` [PATCH 21/33] target/mips: Add emulation of MXU S16LDD S16STD S16LDI S16SDI instructions Siarhei Volkau
2023-06-08 10:42 ` [PATCH 22/33] target/mips: Add emulation of MXU S32MUL S32MULU S32EXTR S32EXTRV insns Siarhei Volkau
2023-06-08 10:42 ` [PATCH 23/33] target/mips: Add emulation of MXU S32ALN S32LUI insns Siarhei Volkau
2023-06-08 10:42 ` [PATCH 24/33] target/mips: Add emulation of MXU D32SARL D32SARW instructions Siarhei Volkau
2023-06-08 10:42 ` [PATCH 25/33] target/mips: Add emulation of MXU D32SLL D32SLR D32SAR instructions Siarhei Volkau
2023-06-08 10:42 ` [PATCH 26/33] target/mips: Add emulation of MXU Q16SLL Q16SLR Q16SAR instructions Siarhei Volkau
2023-06-08 10:42 ` [PATCH 27/33] target/mips: Add emulation of MXU D32/Q16- SLLV/SLRV/SARV instructions Siarhei Volkau
2023-06-08 10:42 ` [PATCH 28/33] target/mips: Add emulation of MXU S32/D16/Q8- MOVZ/MOVN instructions Siarhei Volkau
2023-06-08 10:42 ` [PATCH 29/33] target/mips: Add emulation of MXU Q8MAC Q8MACSU instructions Siarhei Volkau
2023-06-08 10:42 ` [PATCH 30/33] target/mips: Add emulation of MXU Q16SCOP instruction Siarhei Volkau
2023-06-08 10:42 ` [PATCH 31/33] target/mips: Add emulation of MXU Q8MADL instruction Siarhei Volkau
2023-06-08 10:42 ` [PATCH 32/33] target/mips: Add emulation of MXU S32SFL instruction Siarhei Volkau
2023-06-08 10:42 ` [PATCH 33/33] target/mips: Add emulation of MXU Q8SAD instruction Siarhei Volkau
2023-07-10 19:28 ` [PATCH 00/33] target/mips: Finalise the Ingenic MXU ASE support Philippe Mathieu-Daudé
2023-07-20 16:12 ` Siarhei Volkau
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