From: Aaron Lindsay <aaron@os.amperecomputing.com>
To: qemu-devel@nongnu.org, qemu-arm@nongnu.org,
"Richard Henderson" <richard.henderson@linaro.org>,
"Vincent Dehors" <vincent.dehors@smile.fr>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Peter Maydell" <peter.maydell@linaro.org>
Cc: Aaron Lindsay <aaron@os.amperecomputing.com>
Subject: [PATCH v3 1/8] target/arm: Add ID_AA64ISAR2_EL1
Date: Fri, 9 Jun 2023 13:23:17 -0400 [thread overview]
Message-ID: <20230609172324.982888-2-aaron@os.amperecomputing.com> (raw)
In-Reply-To: <20230609172324.982888-1-aaron@os.amperecomputing.com>
Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
---
target/arm/cpu.h | 1 +
target/arm/helper.c | 4 ++--
target/arm/hvf/hvf.c | 1 +
target/arm/kvm64.c | 2 ++
4 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 36c608f0e6..df04c9a9ab 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1023,6 +1023,7 @@ struct ArchCPU {
uint32_t dbgdevid1;
uint64_t id_aa64isar0;
uint64_t id_aa64isar1;
+ uint64_t id_aa64isar2;
uint64_t id_aa64pfr0;
uint64_t id_aa64pfr1;
uint64_t id_aa64mmfr0;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d4bee43bd0..4ced2f71e5 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8204,11 +8204,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
.resetvalue = cpu->isar.id_aa64isar1 },
- { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
+ { .name = "ID_AA64ISAR2_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
.access = PL1_R, .type = ARM_CP_CONST,
.accessfn = access_aa64_tid3,
- .resetvalue = 0 },
+ .resetvalue = cpu->isar.id_aa64isar2 },
{ .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
.access = PL1_R, .type = ARM_CP_CONST,
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 8f72624586..bf567b24db 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -847,6 +847,7 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
{ HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_aa64dfr1 },
{ HV_SYS_REG_ID_AA64ISAR0_EL1, &host_isar.id_aa64isar0 },
{ HV_SYS_REG_ID_AA64ISAR1_EL1, &host_isar.id_aa64isar1 },
+ { HV_SYS_REG_ID_AA64ISAR2_EL1, &host_isar.id_aa64isar2 },
{ HV_SYS_REG_ID_AA64MMFR0_EL1, &host_isar.id_aa64mmfr0 },
{ HV_SYS_REG_ID_AA64MMFR1_EL1, &host_isar.id_aa64mmfr1 },
{ HV_SYS_REG_ID_AA64MMFR2_EL1, &host_isar.id_aa64mmfr2 },
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index 94bbd9661f..e2d05d7fc0 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -306,6 +306,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
ARM64_SYS_REG(3, 0, 0, 6, 0));
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1,
ARM64_SYS_REG(3, 0, 0, 6, 1));
+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar2,
+ ARM64_SYS_REG(3, 0, 0, 6, 2));
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0,
ARM64_SYS_REG(3, 0, 0, 7, 0));
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1,
--
2.25.1
next prev parent reply other threads:[~2023-06-09 17:25 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-09 17:23 [PATCH v3 0/8] Implement Most ARMv8.3 Pointer Authentication Features Aaron Lindsay
2023-06-09 17:23 ` Aaron Lindsay [this message]
2023-06-09 20:49 ` [PATCH v3 1/8] target/arm: Add ID_AA64ISAR2_EL1 Richard Henderson
2023-06-12 13:18 ` Aaron Lindsay
2023-06-19 10:51 ` Peter Maydell
2023-06-30 17:51 ` Richard Henderson
2023-06-09 17:23 ` [PATCH v3 2/8] target/arm: v8.3 PAC ID_AA64ISAR[12] feature-detection Aaron Lindsay
2023-06-09 20:51 ` Richard Henderson
2023-06-12 13:19 ` Aaron Lindsay
2023-06-09 17:23 ` [PATCH v3 3/8] target/arm: Implement v8.3 QARMA3 PAC cipher Aaron Lindsay
2023-06-09 17:23 ` [PATCH v3 4/8] target/arm: Implement v8.3 EnhancedPAC Aaron Lindsay
2023-06-09 17:23 ` [PATCH v3 5/8] target/arm: Implement v8.3 Pauth2 Aaron Lindsay
2023-06-09 17:23 ` [PATCH v3 6/8] targer/arm: Inform helpers whether a PAC instruction is 'combined' Aaron Lindsay
2023-06-09 17:23 ` [PATCH v3 7/8] target/arm: Implement v8.3 FPAC and FPACCOMBINE Aaron Lindsay
2023-07-04 13:40 ` Peter Maydell
2023-06-09 17:23 ` [PATCH v3 8/8] target/arm: Add CPU property for QARMA3, enable FPACCombined by default Aaron Lindsay
2023-07-04 13:43 ` Peter Maydell
2023-07-04 15:01 ` [PATCH v3 0/8] Implement Most ARMv8.3 Pointer Authentication Features Peter Maydell
-- strict thread matches above, loose matches on Subject: below --
2023-03-22 20:25 Aaron Lindsay
2023-03-22 20:25 ` [PATCH v3 1/8] target/arm: Add ID_AA64ISAR2_EL1 Aaron Lindsay
2023-03-23 17:33 ` Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230609172324.982888-2-aaron@os.amperecomputing.com \
--to=aaron@os.amperecomputing.com \
--cc=alex.bennee@linaro.org \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=vincent.dehors@smile.fr \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).