From: Alistair Francis <alistair23@gmail.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
LIU Zhiwei <zhiwei_liu@linux.alibaba.com>,
Weiwei Li <liweiwei@iscas.ac.cn>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 09/60] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers
Date: Wed, 14 Jun 2023 11:19:26 +1000 [thread overview]
Message-ID: <20230614012017.3100663-10-alistair.francis@wdc.com> (raw)
In-Reply-To: <20230614012017.3100663-1-alistair.francis@wdc.com>
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
We're doing env->priv_spec validation and assignment at the start of
riscv_cpu_realize(), which is fine, but then we're doing a force disable
on extensions that aren't compatible with the priv version.
This second step is being done too early. The disabled extensions might be
re-enabled again in riscv_cpu_validate_set_extensions() by accident. A
better place to put this code is at the end of
riscv_cpu_validate_set_extensions() after all the validations are
completed.
Add a new helper, riscv_cpu_disable_priv_spec_isa_exts(), to disable the
extesions after the validation is done. While we're at it, create a
riscv_cpu_validate_priv_spec() helper to host all env->priv_spec related
validation to unclog riscv_cpu_realize a bit.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230517135714.211809-8-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 91 ++++++++++++++++++++++++++++------------------
1 file changed, 56 insertions(+), 35 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 81a785d525..a0589abb16 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -864,6 +864,52 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
env->vext_ver = vext_version;
}
+static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
+{
+ CPURISCVState *env = &cpu->env;
+ int priv_version = -1;
+
+ if (cpu->cfg.priv_spec) {
+ if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
+ priv_version = PRIV_VERSION_1_12_0;
+ } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
+ priv_version = PRIV_VERSION_1_11_0;
+ } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
+ priv_version = PRIV_VERSION_1_10_0;
+ } else {
+ error_setg(errp,
+ "Unsupported privilege spec version '%s'",
+ cpu->cfg.priv_spec);
+ return;
+ }
+
+ env->priv_ver = priv_version;
+ }
+}
+
+static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
+{
+ CPURISCVState *env = &cpu->env;
+ int i;
+
+ /* Force disable extensions if priv spec version does not match */
+ for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
+ if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) &&
+ (env->priv_ver < isa_edata_arr[i].min_version)) {
+ isa_ext_update_enabled(cpu, &isa_edata_arr[i], false);
+#ifndef CONFIG_USER_ONLY
+ warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
+ " because privilege spec version does not match",
+ isa_edata_arr[i].name, env->mhartid);
+#else
+ warn_report("disabling %s extension because "
+ "privilege spec version does not match",
+ isa_edata_arr[i].name);
+#endif
+ }
+ }
+}
+
/*
* Check consistency between chosen extensions while setting
* cpu->cfg accordingly.
@@ -1082,6 +1128,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
cpu->cfg.ext_zksed = true;
cpu->cfg.ext_zksh = true;
}
+
+ /*
+ * Disable isa extensions based on priv spec after we
+ * validated and set everything we need.
+ */
+ riscv_cpu_disable_priv_spec_isa_exts(cpu);
}
#ifndef CONFIG_USER_ONLY
@@ -1181,7 +1233,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
CPURISCVState *env = &cpu->env;
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
CPUClass *cc = CPU_CLASS(mcc);
- int i, priv_version = -1;
Error *local_err = NULL;
cpu_exec_realizefn(cs, &local_err);
@@ -1190,23 +1241,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
return;
}
- if (cpu->cfg.priv_spec) {
- if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
- priv_version = PRIV_VERSION_1_12_0;
- } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
- priv_version = PRIV_VERSION_1_11_0;
- } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
- priv_version = PRIV_VERSION_1_10_0;
- } else {
- error_setg(errp,
- "Unsupported privilege spec version '%s'",
- cpu->cfg.priv_spec);
- return;
- }
- }
-
- if (priv_version >= PRIV_VERSION_1_10_0) {
- env->priv_ver = priv_version;
+ riscv_cpu_validate_priv_spec(cpu, &local_err);
+ if (local_err != NULL) {
+ error_propagate(errp, local_err);
+ return;
}
riscv_cpu_validate_misa_priv(env, &local_err);
@@ -1215,23 +1253,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
return;
}
- /* Force disable extensions if priv spec version does not match */
- for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
- if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) &&
- (env->priv_ver < isa_edata_arr[i].min_version)) {
- isa_ext_update_enabled(cpu, &isa_edata_arr[i], false);
-#ifndef CONFIG_USER_ONLY
- warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
- " because privilege spec version does not match",
- isa_edata_arr[i].name, env->mhartid);
-#else
- warn_report("disabling %s extension because "
- "privilege spec version does not match",
- isa_edata_arr[i].name);
-#endif
- }
- }
-
if (cpu->cfg.epmp && !cpu->cfg.pmp) {
/*
* Enhanced PMP should only be available
--
2.40.1
next prev parent reply other threads:[~2023-06-14 1:25 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
2023-06-14 1:19 ` [PULL 01/60] target/riscv/vector_helper.c: skip set tail when vta is zero Alistair Francis
2023-06-14 1:19 ` [PULL 02/60] target/riscv: Move zc* out of the experimental properties Alistair Francis
2023-06-14 1:19 ` [PULL 03/60] target/riscv/cpu.c: add riscv_cpu_validate_v() Alistair Francis
2023-06-14 1:19 ` [PULL 04/60] target/riscv/cpu.c: remove set_vext_version() Alistair Francis
2023-06-14 1:19 ` [PULL 05/60] target/riscv/cpu.c: remove set_priv_version() Alistair Francis
2023-06-14 1:19 ` [PULL 06/60] target/riscv: add PRIV_VERSION_LATEST Alistair Francis
2023-06-14 1:19 ` [PULL 07/60] target/riscv: Mask the implicitly enabled extensions in isa_string based on priv version Alistair Francis
2023-06-14 1:19 ` [PULL 08/60] target/riscv: Update check for Zca/Zcf/Zcd Alistair Francis
2023-06-14 1:19 ` Alistair Francis [this message]
2023-06-14 1:19 ` [PULL 10/60] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl() Alistair Francis
2023-06-14 1:19 ` [PULL 11/60] target/riscv/cpu.c: validate extensions before riscv_timer_init() Alistair Francis
2023-06-14 1:19 ` [PULL 12/60] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init() Alistair Francis
2023-06-14 1:19 ` [PULL 13/60] target/riscv: rework write_misa() Alistair Francis
2023-06-14 1:19 ` [PULL 14/60] target/riscv: Update pmp_get_tlb_size() Alistair Francis
2023-06-14 1:19 ` [PULL 15/60] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp Alistair Francis
2023-06-14 1:19 ` [PULL 16/60] target/riscv: Make the short cut really work in pmp_hart_has_privs Alistair Francis
2023-06-14 1:19 ` [PULL 17/60] target/riscv: Change the return type of pmp_hart_has_privs() to bool Alistair Francis
2023-06-14 1:19 ` [PULL 18/60] target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled Alistair Francis
2023-06-14 1:19 ` [PULL 19/60] target/riscv: Remove unused paramters in pmp_hart_has_privs_default() Alistair Francis
2023-06-14 1:19 ` [PULL 20/60] target/riscv: Flush TLB when MMWP or MML bits are changed Alistair Francis
2023-06-14 1:19 ` [PULL 21/60] target/riscv: Update the next rule addr in pmpaddr_csr_write() Alistair Francis
2023-06-14 1:19 ` [PULL 22/60] target/riscv: Flush TLB when pmpaddr is updated Alistair Francis
2023-06-14 1:19 ` [PULL 23/60] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes Alistair Francis
2023-06-14 1:19 ` [PULL 24/60] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write Alistair Francis
2023-06-14 1:19 ` [PULL 25/60] target/riscv: Deny access if access is partially inside the PMP entry Alistair Francis
2023-06-14 1:19 ` [PULL 26/60] hw/riscv/opentitan: Rename machine_[class]_init() functions Alistair Francis
2023-06-14 1:19 ` [PULL 27/60] hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro Alistair Francis
2023-06-14 1:19 ` [PULL 28/60] hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition Alistair Francis
2023-06-14 1:19 ` [PULL 29/60] hw/riscv/opentitan: Explicit machine type definition Alistair Francis
2023-06-14 1:19 ` [PULL 30/60] hw/riscv/opentitan: Correct OpenTitanState parent type/size Alistair Francis
2023-06-14 1:19 ` [PULL 31/60] hw/riscv: qemu crash when NUMA nodes exceed available CPUs Alistair Francis
2023-06-14 1:19 ` [PULL 32/60] target/riscv: Fix pointer mask transformation for vector address Alistair Francis
2023-06-14 1:19 ` [PULL 33/60] target/riscv: Update cur_pmmask/base when xl changes Alistair Francis
2023-06-14 1:19 ` [PULL 34/60] target/riscv: smstateen check for fcsr Alistair Francis
2023-06-14 1:19 ` [PULL 35/60] target/riscv: Reuse tb->flags.FS Alistair Francis
2023-06-14 1:19 ` [PULL 36/60] target/riscv: smstateen knobs Alistair Francis
2023-06-14 1:19 ` [PULL 37/60] disas: Change type of disassemble_info.target_info to pointer Alistair Francis
2023-06-14 1:19 ` [PULL 38/60] target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h Alistair Francis
2023-06-14 1:19 ` [PULL 39/60] target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info Alistair Francis
2023-06-14 1:19 ` [PULL 40/60] disas/riscv.c: Support disas for Zcm* extensions Alistair Francis
2023-06-14 1:19 ` [PULL 41/60] disas/riscv.c: Support disas for Z*inx extensions Alistair Francis
2023-06-14 1:19 ` [PULL 42/60] disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions Alistair Francis
2023-06-14 1:20 ` [PULL 43/60] disas/riscv.c: Fix lines with over 80 characters Alistair Francis
2023-06-14 1:20 ` [PULL 44/60] disas/riscv.c: Remove redundant parentheses Alistair Francis
2023-06-14 1:20 ` [PULL 45/60] target/riscv: Fix target address to update badaddr Alistair Francis
2023-06-14 1:20 ` [PULL 46/60] target/riscv: Introduce cur_insn_len into DisasContext Alistair Francis
2023-06-14 1:20 ` [PULL 47/60] target/riscv: Change gen_goto_tb to work on displacements Alistair Francis
2023-06-14 1:20 ` [PULL 48/60] target/riscv: Change gen_set_pc_imm to gen_update_pc Alistair Francis
2023-06-14 1:20 ` [PULL 49/60] target/riscv: Use true diff for gen_pc_plus_diff Alistair Francis
2023-06-14 1:20 ` [PULL 50/60] target/riscv: Enable PC-relative translation Alistair Francis
2023-06-14 1:20 ` [PULL 51/60] target/riscv: Remove pc_succ_insn from DisasContext Alistair Francis
2023-06-14 1:20 ` [PULL 52/60] hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none" Alistair Francis
2023-06-14 1:20 ` [PULL 53/60] riscv/virt: Support using pflash via -blockdev option Alistair Francis
2023-06-14 1:20 ` [PULL 54/60] docs/system: riscv: Add pflash usage details Alistair Francis
2023-06-14 1:20 ` [PULL 55/60] util/log: Add vector registers to log Alistair Francis
2023-06-14 1:20 ` [PULL 56/60] target/riscv: Fix initialized value for cur_pmmask Alistair Francis
2023-06-14 1:20 ` [PULL 57/60] target/riscv/vector_helper.c: clean up reference of MTYPE Alistair Francis
2023-06-14 1:20 ` [PULL 58/60] target/riscv/vector_helper.c: Remove the check for extra tail elements Alistair Francis
2023-06-14 1:20 ` [PULL 59/60] target/riscv: Smepmp: Return error when access permission not allowed in PMP Alistair Francis
2023-06-14 1:20 ` [PULL 60/60] hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only Alistair Francis
2023-06-14 4:39 ` [PULL 00/60] riscv-to-apply queue Richard Henderson
2023-06-14 12:17 ` Michael Tokarev
2023-06-15 4:03 ` Alistair Francis
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