From: Alistair Francis <alistair23@gmail.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, "Sunil V L" <sunilvl@ventanamicro.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Alistair Francis" <alistair.francis@wdc.com>
Subject: [PULL 54/60] docs/system: riscv: Add pflash usage details
Date: Wed, 14 Jun 2023 11:20:11 +1000 [thread overview]
Message-ID: <20230614012017.3100663-55-alistair.francis@wdc.com> (raw)
In-Reply-To: <20230614012017.3100663-1-alistair.francis@wdc.com>
From: Sunil V L <sunilvl@ventanamicro.com>
pflash devices can be used in virt machine for different
purposes like for ROM code or S-mode FW payload. Add a
section in the documentation on how to use pflash devices
for different purposes.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230601045910.18646-4-sunilvl@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
docs/system/riscv/virt.rst | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
index 4b16e41d7f..b33f45e5b3 100644
--- a/docs/system/riscv/virt.rst
+++ b/docs/system/riscv/virt.rst
@@ -53,6 +53,37 @@ with the default OpenSBI firmware image as the -bios. It also supports
the recommended RISC-V bootflow: U-Boot SPL (M-mode) loads OpenSBI fw_dynamic
firmware and U-Boot proper (S-mode), using the standard -bios functionality.
+Using flash devices
+-------------------
+
+By default, the first flash device (pflash0) is expected to contain
+S-mode firmware code. It can be configured as read-only, with the
+second flash device (pflash1) available to store configuration data.
+
+For example, booting edk2 looks like
+
+.. code-block:: bash
+
+ $ qemu-system-riscv64 \
+ -blockdev node-name=pflash0,driver=file,read-only=on,filename=<edk2_code> \
+ -blockdev node-name=pflash1,driver=file,filename=<edk2_vars> \
+ -M virt,pflash0=pflash0,pflash1=pflash1 \
+ ... other args ....
+
+For TCG guests only, it is also possible to boot M-mode firmware from
+the first flash device (pflash0) by additionally passing ``-bios
+none``, as in
+
+.. code-block:: bash
+
+ $ qemu-system-riscv64 \
+ -bios none \
+ -blockdev node-name=pflash0,driver=file,read-only=on,filename=<m_mode_code> \
+ -M virt,pflash0=pflash0 \
+ ... other args ....
+
+Firmware images used for pflash must be exactly 32 MiB in size.
+
Machine-specific options
------------------------
--
2.40.1
next prev parent reply other threads:[~2023-06-14 1:27 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-14 1:19 [PULL 00/60] riscv-to-apply queue Alistair Francis
2023-06-14 1:19 ` [PULL 01/60] target/riscv/vector_helper.c: skip set tail when vta is zero Alistair Francis
2023-06-14 1:19 ` [PULL 02/60] target/riscv: Move zc* out of the experimental properties Alistair Francis
2023-06-14 1:19 ` [PULL 03/60] target/riscv/cpu.c: add riscv_cpu_validate_v() Alistair Francis
2023-06-14 1:19 ` [PULL 04/60] target/riscv/cpu.c: remove set_vext_version() Alistair Francis
2023-06-14 1:19 ` [PULL 05/60] target/riscv/cpu.c: remove set_priv_version() Alistair Francis
2023-06-14 1:19 ` [PULL 06/60] target/riscv: add PRIV_VERSION_LATEST Alistair Francis
2023-06-14 1:19 ` [PULL 07/60] target/riscv: Mask the implicitly enabled extensions in isa_string based on priv version Alistair Francis
2023-06-14 1:19 ` [PULL 08/60] target/riscv: Update check for Zca/Zcf/Zcd Alistair Francis
2023-06-14 1:19 ` [PULL 09/60] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers Alistair Francis
2023-06-14 1:19 ` [PULL 10/60] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl() Alistair Francis
2023-06-14 1:19 ` [PULL 11/60] target/riscv/cpu.c: validate extensions before riscv_timer_init() Alistair Francis
2023-06-14 1:19 ` [PULL 12/60] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init() Alistair Francis
2023-06-14 1:19 ` [PULL 13/60] target/riscv: rework write_misa() Alistair Francis
2023-06-14 1:19 ` [PULL 14/60] target/riscv: Update pmp_get_tlb_size() Alistair Francis
2023-06-14 1:19 ` [PULL 15/60] target/riscv: Move pmp_get_tlb_size apart from get_physical_address_pmp Alistair Francis
2023-06-14 1:19 ` [PULL 16/60] target/riscv: Make the short cut really work in pmp_hart_has_privs Alistair Francis
2023-06-14 1:19 ` [PULL 17/60] target/riscv: Change the return type of pmp_hart_has_privs() to bool Alistair Francis
2023-06-14 1:19 ` [PULL 18/60] target/riscv: Make RLB/MML/MMWP bits writable only when Smepmp is enabled Alistair Francis
2023-06-14 1:19 ` [PULL 19/60] target/riscv: Remove unused paramters in pmp_hart_has_privs_default() Alistair Francis
2023-06-14 1:19 ` [PULL 20/60] target/riscv: Flush TLB when MMWP or MML bits are changed Alistair Francis
2023-06-14 1:19 ` [PULL 21/60] target/riscv: Update the next rule addr in pmpaddr_csr_write() Alistair Francis
2023-06-14 1:19 ` [PULL 22/60] target/riscv: Flush TLB when pmpaddr is updated Alistair Francis
2023-06-14 1:19 ` [PULL 23/60] target/riscv: Flush TLB only when pmpcfg/pmpaddr really changes Alistair Francis
2023-06-14 1:19 ` [PULL 24/60] target/riscv: Separate pmp_update_rule() in pmpcfg_csr_write Alistair Francis
2023-06-14 1:19 ` [PULL 25/60] target/riscv: Deny access if access is partially inside the PMP entry Alistair Francis
2023-06-14 1:19 ` [PULL 26/60] hw/riscv/opentitan: Rename machine_[class]_init() functions Alistair Francis
2023-06-14 1:19 ` [PULL 27/60] hw/riscv/opentitan: Declare QOM types using DEFINE_TYPES() macro Alistair Francis
2023-06-14 1:19 ` [PULL 28/60] hw/riscv/opentitan: Add TYPE_OPENTITAN_MACHINE definition Alistair Francis
2023-06-14 1:19 ` [PULL 29/60] hw/riscv/opentitan: Explicit machine type definition Alistair Francis
2023-06-14 1:19 ` [PULL 30/60] hw/riscv/opentitan: Correct OpenTitanState parent type/size Alistair Francis
2023-06-14 1:19 ` [PULL 31/60] hw/riscv: qemu crash when NUMA nodes exceed available CPUs Alistair Francis
2023-06-14 1:19 ` [PULL 32/60] target/riscv: Fix pointer mask transformation for vector address Alistair Francis
2023-06-14 1:19 ` [PULL 33/60] target/riscv: Update cur_pmmask/base when xl changes Alistair Francis
2023-06-14 1:19 ` [PULL 34/60] target/riscv: smstateen check for fcsr Alistair Francis
2023-06-14 1:19 ` [PULL 35/60] target/riscv: Reuse tb->flags.FS Alistair Francis
2023-06-14 1:19 ` [PULL 36/60] target/riscv: smstateen knobs Alistair Francis
2023-06-14 1:19 ` [PULL 37/60] disas: Change type of disassemble_info.target_info to pointer Alistair Francis
2023-06-14 1:19 ` [PULL 38/60] target/riscv: Split RISCVCPUConfig declarations from cpu.h into cpu_cfg.h Alistair Francis
2023-06-14 1:19 ` [PULL 39/60] target/riscv: Pass RISCVCPUConfig as target_info to disassemble_info Alistair Francis
2023-06-14 1:19 ` [PULL 40/60] disas/riscv.c: Support disas for Zcm* extensions Alistair Francis
2023-06-14 1:19 ` [PULL 41/60] disas/riscv.c: Support disas for Z*inx extensions Alistair Francis
2023-06-14 1:19 ` [PULL 42/60] disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructions Alistair Francis
2023-06-14 1:20 ` [PULL 43/60] disas/riscv.c: Fix lines with over 80 characters Alistair Francis
2023-06-14 1:20 ` [PULL 44/60] disas/riscv.c: Remove redundant parentheses Alistair Francis
2023-06-14 1:20 ` [PULL 45/60] target/riscv: Fix target address to update badaddr Alistair Francis
2023-06-14 1:20 ` [PULL 46/60] target/riscv: Introduce cur_insn_len into DisasContext Alistair Francis
2023-06-14 1:20 ` [PULL 47/60] target/riscv: Change gen_goto_tb to work on displacements Alistair Francis
2023-06-14 1:20 ` [PULL 48/60] target/riscv: Change gen_set_pc_imm to gen_update_pc Alistair Francis
2023-06-14 1:20 ` [PULL 49/60] target/riscv: Use true diff for gen_pc_plus_diff Alistair Francis
2023-06-14 1:20 ` [PULL 50/60] target/riscv: Enable PC-relative translation Alistair Francis
2023-06-14 1:20 ` [PULL 51/60] target/riscv: Remove pc_succ_insn from DisasContext Alistair Francis
2023-06-14 1:20 ` [PULL 52/60] hw/riscv: virt: Assume M-mode FW in pflash0 only when "-bios none" Alistair Francis
2023-06-14 1:20 ` [PULL 53/60] riscv/virt: Support using pflash via -blockdev option Alistair Francis
2023-06-14 1:20 ` Alistair Francis [this message]
2023-06-14 1:20 ` [PULL 55/60] util/log: Add vector registers to log Alistair Francis
2023-06-14 1:20 ` [PULL 56/60] target/riscv: Fix initialized value for cur_pmmask Alistair Francis
2023-06-14 1:20 ` [PULL 57/60] target/riscv/vector_helper.c: clean up reference of MTYPE Alistair Francis
2023-06-14 1:20 ` [PULL 58/60] target/riscv/vector_helper.c: Remove the check for extra tail elements Alistair Francis
2023-06-14 1:20 ` [PULL 59/60] target/riscv: Smepmp: Return error when access permission not allowed in PMP Alistair Francis
2023-06-14 1:20 ` [PULL 60/60] hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only Alistair Francis
2023-06-14 4:39 ` [PULL 00/60] riscv-to-apply queue Richard Henderson
2023-06-14 12:17 ` Michael Tokarev
2023-06-15 4:03 ` Alistair Francis
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