* [PATCH 0/2] target/riscv: Fix the xlen for data address when MPRV=1
@ 2023-06-14 3:25 Weiwei Li
2023-06-14 3:25 ` [PATCH 1/2] target/riscv: Add additional xlen for " Weiwei Li
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Weiwei Li @ 2023-06-14 3:25 UTC (permalink / raw)
To: qemu-riscv, qemu-devel
Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu,
wangjunqiang, lazyparser, Weiwei Li
Currently, we use the current env->xl as the xlen for address. However, the xlen for data address should be changed to the xlen related to MPP when MPRV=1.
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-addr-xl-upstream
Weiwei Li (2):
target/riscv: Add additional xlen for address when MPRV=1
target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV
target/riscv/cpu.h | 49 +++++++++++++++++++++++++++++++++------
target/riscv/cpu_helper.c | 8 +++++--
target/riscv/csr.c | 27 +++++++++++++++------
target/riscv/translate.c | 13 ++++++++++-
4 files changed, 80 insertions(+), 17 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 1/2] target/riscv: Add additional xlen for address when MPRV=1 2023-06-14 3:25 [PATCH 0/2] target/riscv: Fix the xlen for data address when MPRV=1 Weiwei Li @ 2023-06-14 3:25 ` Weiwei Li 2023-06-14 9:18 ` Daniel Henrique Barboza 2023-06-14 3:25 ` [PATCH 2/2] target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV Weiwei Li 2023-06-23 2:22 ` [PATCH 0/2] target/riscv: Fix the xlen for data address when MPRV=1 Alistair Francis 2 siblings, 1 reply; 6+ messages in thread From: Weiwei Li @ 2023-06-14 3:25 UTC (permalink / raw) To: qemu-riscv, qemu-devel Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu, wangjunqiang, lazyparser, Weiwei Li As specified in privilege spec:"When MPRV=1, load and store memory addresses are treated as though the current XLEN were set to MPP’s XLEN". So the xlen for address may be different from current xlen. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> --- target/riscv/cpu.h | 49 +++++++++++++++++++++++++++++++++------ target/riscv/cpu_helper.c | 1 + target/riscv/translate.c | 13 ++++++++++- 3 files changed, 55 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e3e08d315f..cc20ee25a7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -498,6 +498,7 @@ FIELD(TB_FLAGS, ITRIGGER, 22, 1) /* Virtual mode enabled */ FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) FIELD(TB_FLAGS, PRIV, 24, 2) +FIELD(TB_FLAGS, AXL, 26, 2) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) @@ -514,13 +515,20 @@ static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) return &env_archcpu(env)->cfg; } -#if defined(TARGET_RISCV32) -#define cpu_recompute_xl(env) ((void)(env), MXL_RV32) -#else -static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) +#if !defined(CONFIG_USER_ONLY) +static inline int cpu_address_mode(CPURISCVState *env) +{ + int mode = env->priv; + + if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { + mode = get_field(env->mstatus, MSTATUS_MPP); + } + return mode; +} + +static inline RISCVMXL cpu_get_xl(CPURISCVState *env, target_ulong mode) { RISCVMXL xl = env->misa_mxl; -#if !defined(CONFIG_USER_ONLY) /* * When emulating a 32-bit-only cpu, use RV32. * When emulating a 64-bit cpu, and MXL has been reduced to RV32, @@ -528,7 +536,7 @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) * back to RV64 for lower privs. */ if (xl != MXL_RV32) { - switch (env->priv) { + switch (mode) { case PRV_M: break; case PRV_U: @@ -539,11 +547,38 @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) break; } } -#endif return xl; } #endif +#if defined(TARGET_RISCV32) +#define cpu_recompute_xl(env) ((void)(env), MXL_RV32) +#else +static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) +{ +#if !defined(CONFIG_USER_ONLY) + return cpu_get_xl(env, env->priv); +#else + return env->misa_mxl; +#endif +} +#endif + +#if defined(TARGET_RISCV32) +#define cpu_address_xl(env) ((void)(env), MXL_RV32) +#else +static inline RISCVMXL cpu_address_xl(CPURISCVState *env) +{ +#ifdef CONFIG_USER_ONLY + return env->xl; +#else + int mode = cpu_address_mode(env); + + return cpu_get_xl(env, mode); +#endif +} +#endif + static inline int riscv_cpu_xlen(CPURISCVState *env) { return 16 << env->xl; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 90cef9856d..f85113a3db 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -134,6 +134,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, flags = FIELD_DP32(flags, TB_FLAGS, FS, fs); flags = FIELD_DP32(flags, TB_FLAGS, VS, vs); flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); + flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); if (env->cur_pmmask != 0) { flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 8a33da811e..4bf61766b6 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -64,6 +64,7 @@ typedef struct DisasContext { target_ulong priv_ver; RISCVMXL misa_mxl_max; RISCVMXL xl; + RISCVMXL address_xl; uint32_t misa_ext; uint32_t opcode; RISCVExtStatus mstatus_fs; @@ -152,6 +153,14 @@ MATERIALISE_EXT_PREDICATE(XVentanaCondOps); #define get_xl(ctx) ((ctx)->xl) #endif +#ifdef TARGET_RISCV32 +#define get_address_xl(ctx) MXL_RV32 +#elif defined(CONFIG_USER_ONLY) +#define get_address_xl(ctx) MXL_RV64 +#else +#define get_address_xl(ctx) ((ctx)->address_xl) +#endif + /* The word size for this machine mode. */ static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) { @@ -598,12 +607,13 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm) tcg_gen_addi_tl(addr, src1, imm); if (ctx->pm_mask_enabled) { tcg_gen_andc_tl(addr, addr, pm_mask); - } else if (get_xl(ctx) == MXL_RV32) { + } else if (get_address_xl(ctx) == MXL_RV32) { tcg_gen_ext32u_tl(addr, addr); } if (ctx->pm_base_enabled) { tcg_gen_or_tl(addr, addr, pm_base); } + return addr; } @@ -1200,6 +1210,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); ctx->misa_mxl_max = env->misa_mxl_max; ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); + ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL); ctx->cs = cs; ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); -- 2.25.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] target/riscv: Add additional xlen for address when MPRV=1 2023-06-14 3:25 ` [PATCH 1/2] target/riscv: Add additional xlen for " Weiwei Li @ 2023-06-14 9:18 ` Daniel Henrique Barboza 0 siblings, 0 replies; 6+ messages in thread From: Daniel Henrique Barboza @ 2023-06-14 9:18 UTC (permalink / raw) To: Weiwei Li, qemu-riscv, qemu-devel Cc: palmer, alistair.francis, bin.meng, zhiwei_liu, wangjunqiang, lazyparser On 6/14/23 00:25, Weiwei Li wrote: > As specified in privilege spec:"When MPRV=1, load and store memory > addresses are treated as though the current XLEN were set to MPP’s > XLEN". So the xlen for address may be different from current xlen. > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > target/riscv/cpu.h | 49 +++++++++++++++++++++++++++++++++------ > target/riscv/cpu_helper.c | 1 + > target/riscv/translate.c | 13 ++++++++++- > 3 files changed, 55 insertions(+), 8 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index e3e08d315f..cc20ee25a7 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -498,6 +498,7 @@ FIELD(TB_FLAGS, ITRIGGER, 22, 1) > /* Virtual mode enabled */ > FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) > FIELD(TB_FLAGS, PRIV, 24, 2) > +FIELD(TB_FLAGS, AXL, 26, 2) > > #ifdef TARGET_RISCV32 > #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) > @@ -514,13 +515,20 @@ static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) > return &env_archcpu(env)->cfg; > } > > -#if defined(TARGET_RISCV32) > -#define cpu_recompute_xl(env) ((void)(env), MXL_RV32) > -#else > -static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) > +#if !defined(CONFIG_USER_ONLY) > +static inline int cpu_address_mode(CPURISCVState *env) > +{ > + int mode = env->priv; > + > + if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { > + mode = get_field(env->mstatus, MSTATUS_MPP); > + } > + return mode; > +} > + > +static inline RISCVMXL cpu_get_xl(CPURISCVState *env, target_ulong mode) > { > RISCVMXL xl = env->misa_mxl; > -#if !defined(CONFIG_USER_ONLY) > /* > * When emulating a 32-bit-only cpu, use RV32. > * When emulating a 64-bit cpu, and MXL has been reduced to RV32, > @@ -528,7 +536,7 @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) > * back to RV64 for lower privs. > */ > if (xl != MXL_RV32) { > - switch (env->priv) { > + switch (mode) { > case PRV_M: > break; > case PRV_U: > @@ -539,11 +547,38 @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) > break; > } > } > -#endif > return xl; > } > #endif > > +#if defined(TARGET_RISCV32) > +#define cpu_recompute_xl(env) ((void)(env), MXL_RV32) > +#else > +static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) > +{ > +#if !defined(CONFIG_USER_ONLY) > + return cpu_get_xl(env, env->priv); > +#else > + return env->misa_mxl; > +#endif > +} > +#endif > + > +#if defined(TARGET_RISCV32) > +#define cpu_address_xl(env) ((void)(env), MXL_RV32) > +#else > +static inline RISCVMXL cpu_address_xl(CPURISCVState *env) > +{ > +#ifdef CONFIG_USER_ONLY > + return env->xl; > +#else > + int mode = cpu_address_mode(env); > + > + return cpu_get_xl(env, mode); > +#endif > +} > +#endif > + > static inline int riscv_cpu_xlen(CPURISCVState *env) > { > return 16 << env->xl; > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 90cef9856d..f85113a3db 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -134,6 +134,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, > flags = FIELD_DP32(flags, TB_FLAGS, FS, fs); > flags = FIELD_DP32(flags, TB_FLAGS, VS, vs); > flags = FIELD_DP32(flags, TB_FLAGS, XL, env->xl); > + flags = FIELD_DP32(flags, TB_FLAGS, AXL, cpu_address_xl(env)); > if (env->cur_pmmask != 0) { > flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); > } > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 8a33da811e..4bf61766b6 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -64,6 +64,7 @@ typedef struct DisasContext { > target_ulong priv_ver; > RISCVMXL misa_mxl_max; > RISCVMXL xl; > + RISCVMXL address_xl; > uint32_t misa_ext; > uint32_t opcode; > RISCVExtStatus mstatus_fs; > @@ -152,6 +153,14 @@ MATERIALISE_EXT_PREDICATE(XVentanaCondOps); > #define get_xl(ctx) ((ctx)->xl) > #endif > > +#ifdef TARGET_RISCV32 > +#define get_address_xl(ctx) MXL_RV32 > +#elif defined(CONFIG_USER_ONLY) > +#define get_address_xl(ctx) MXL_RV64 > +#else > +#define get_address_xl(ctx) ((ctx)->address_xl) > +#endif > + > /* The word size for this machine mode. */ > static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) > { > @@ -598,12 +607,13 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm) > tcg_gen_addi_tl(addr, src1, imm); > if (ctx->pm_mask_enabled) { > tcg_gen_andc_tl(addr, addr, pm_mask); > - } else if (get_xl(ctx) == MXL_RV32) { > + } else if (get_address_xl(ctx) == MXL_RV32) { > tcg_gen_ext32u_tl(addr, addr); > } > if (ctx->pm_base_enabled) { > tcg_gen_or_tl(addr, addr, pm_base); > } > + > return addr; > } > > @@ -1200,6 +1210,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) > ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); > ctx->misa_mxl_max = env->misa_mxl_max; > ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); > + ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL); > ctx->cs = cs; > ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); > ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/2] target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV 2023-06-14 3:25 [PATCH 0/2] target/riscv: Fix the xlen for data address when MPRV=1 Weiwei Li 2023-06-14 3:25 ` [PATCH 1/2] target/riscv: Add additional xlen for " Weiwei Li @ 2023-06-14 3:25 ` Weiwei Li 2023-06-14 9:18 ` Daniel Henrique Barboza 2023-06-23 2:22 ` [PATCH 0/2] target/riscv: Fix the xlen for data address when MPRV=1 Alistair Francis 2 siblings, 1 reply; 6+ messages in thread From: Weiwei Li @ 2023-06-14 3:25 UTC (permalink / raw) To: qemu-riscv, qemu-devel Cc: palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu, wangjunqiang, lazyparser, Weiwei Li Pointer mask is also affected by MPRV which means cur_pmbase/pmmask should also take MPRV into consideration. As pointer mask for instruction is not supported currently, so we can directly update cur_pmbase/pmmask based on address related mode and xlen affected by MPRV now. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> --- target/riscv/cpu_helper.c | 7 +++++-- target/riscv/csr.c | 27 ++++++++++++++++++++------- 2 files changed, 25 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f85113a3db..2321f9132f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -148,13 +148,16 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, void riscv_cpu_update_mask(CPURISCVState *env) { target_ulong mask = 0, base = 0; + RISCVMXL xl = env->xl; /* * TODO: Current RVJ spec does not specify * how the extension interacts with XLEN. */ #ifndef CONFIG_USER_ONLY + int mode = cpu_address_mode(env); + xl = cpu_get_xl(env, mode); if (riscv_has_ext(env, RVJ)) { - switch (env->priv) { + switch (mode) { case PRV_M: if (env->mmte & M_PM_ENABLE) { mask = env->mpmmask; @@ -178,7 +181,7 @@ void riscv_cpu_update_mask(CPURISCVState *env) } } #endif - if (env->xl == MXL_RV32) { + if (xl == MXL_RV32) { env->cur_pmmask = mask & UINT32_MAX; env->cur_pmbase = base & UINT32_MAX; } else { diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 58499b5afc..63cc5d7e2d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1335,8 +1335,9 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, */ if (env->debugger) { env->xl = cpu_recompute_xl(env); - riscv_cpu_update_mask(env); } + + riscv_cpu_update_mask(env); return RISCV_EXCP_NONE; } @@ -3639,7 +3640,7 @@ static RISCVException write_mpmmask(CPURISCVState *env, int csrno, uint64_t mstatus; env->mpmmask = val; - if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) { + if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) { env->cur_pmmask = val; } env->mmte |= EXT_STATUS_DIRTY; @@ -3667,8 +3668,11 @@ static RISCVException write_spmmask(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } env->spmmask = val; - if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) { + if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) { env->cur_pmmask = val; + if (cpu_get_xl(env, PRV_S) == MXL_RV32) { + env->cur_pmmask &= UINT32_MAX; + } } env->mmte |= EXT_STATUS_DIRTY; @@ -3695,8 +3699,11 @@ static RISCVException write_upmmask(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } env->upmmask = val; - if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) { + if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) { env->cur_pmmask = val; + if (cpu_get_xl(env, PRV_U) == MXL_RV32) { + env->cur_pmmask &= UINT32_MAX; + } } env->mmte |= EXT_STATUS_DIRTY; @@ -3719,7 +3726,7 @@ static RISCVException write_mpmbase(CPURISCVState *env, int csrno, uint64_t mstatus; env->mpmbase = val; - if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) { + if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) { env->cur_pmbase = val; } env->mmte |= EXT_STATUS_DIRTY; @@ -3747,8 +3754,11 @@ static RISCVException write_spmbase(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } env->spmbase = val; - if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) { + if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) { env->cur_pmbase = val; + if (cpu_get_xl(env, PRV_S) == MXL_RV32) { + env->cur_pmbase &= UINT32_MAX; + } } env->mmte |= EXT_STATUS_DIRTY; @@ -3775,8 +3785,11 @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } env->upmbase = val; - if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) { + if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) { env->cur_pmbase = val; + if (cpu_get_xl(env, PRV_U) == MXL_RV32) { + env->cur_pmbase &= UINT32_MAX; + } } env->mmte |= EXT_STATUS_DIRTY; -- 2.25.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV 2023-06-14 3:25 ` [PATCH 2/2] target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV Weiwei Li @ 2023-06-14 9:18 ` Daniel Henrique Barboza 0 siblings, 0 replies; 6+ messages in thread From: Daniel Henrique Barboza @ 2023-06-14 9:18 UTC (permalink / raw) To: Weiwei Li, qemu-riscv, qemu-devel Cc: palmer, alistair.francis, bin.meng, zhiwei_liu, wangjunqiang, lazyparser On 6/14/23 00:25, Weiwei Li wrote: > Pointer mask is also affected by MPRV which means cur_pmbase/pmmask > should also take MPRV into consideration. As pointer mask for instruction > is not supported currently, so we can directly update cur_pmbase/pmmask > based on address related mode and xlen affected by MPRV now. > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > target/riscv/cpu_helper.c | 7 +++++-- > target/riscv/csr.c | 27 ++++++++++++++++++++------- > 2 files changed, 25 insertions(+), 9 deletions(-) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index f85113a3db..2321f9132f 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -148,13 +148,16 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, > void riscv_cpu_update_mask(CPURISCVState *env) > { > target_ulong mask = 0, base = 0; > + RISCVMXL xl = env->xl; > /* > * TODO: Current RVJ spec does not specify > * how the extension interacts with XLEN. > */ > #ifndef CONFIG_USER_ONLY > + int mode = cpu_address_mode(env); > + xl = cpu_get_xl(env, mode); > if (riscv_has_ext(env, RVJ)) { > - switch (env->priv) { > + switch (mode) { > case PRV_M: > if (env->mmte & M_PM_ENABLE) { > mask = env->mpmmask; > @@ -178,7 +181,7 @@ void riscv_cpu_update_mask(CPURISCVState *env) > } > } > #endif > - if (env->xl == MXL_RV32) { > + if (xl == MXL_RV32) { > env->cur_pmmask = mask & UINT32_MAX; > env->cur_pmbase = base & UINT32_MAX; > } else { > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 58499b5afc..63cc5d7e2d 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -1335,8 +1335,9 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, > */ > if (env->debugger) { > env->xl = cpu_recompute_xl(env); > - riscv_cpu_update_mask(env); > } > + > + riscv_cpu_update_mask(env); > return RISCV_EXCP_NONE; > } > > @@ -3639,7 +3640,7 @@ static RISCVException write_mpmmask(CPURISCVState *env, int csrno, > uint64_t mstatus; > > env->mpmmask = val; > - if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) { > + if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) { > env->cur_pmmask = val; > } > env->mmte |= EXT_STATUS_DIRTY; > @@ -3667,8 +3668,11 @@ static RISCVException write_spmmask(CPURISCVState *env, int csrno, > return RISCV_EXCP_NONE; > } > env->spmmask = val; > - if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) { > + if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) { > env->cur_pmmask = val; > + if (cpu_get_xl(env, PRV_S) == MXL_RV32) { > + env->cur_pmmask &= UINT32_MAX; > + } > } > env->mmte |= EXT_STATUS_DIRTY; > > @@ -3695,8 +3699,11 @@ static RISCVException write_upmmask(CPURISCVState *env, int csrno, > return RISCV_EXCP_NONE; > } > env->upmmask = val; > - if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) { > + if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) { > env->cur_pmmask = val; > + if (cpu_get_xl(env, PRV_U) == MXL_RV32) { > + env->cur_pmmask &= UINT32_MAX; > + } > } > env->mmte |= EXT_STATUS_DIRTY; > > @@ -3719,7 +3726,7 @@ static RISCVException write_mpmbase(CPURISCVState *env, int csrno, > uint64_t mstatus; > > env->mpmbase = val; > - if ((env->priv == PRV_M) && (env->mmte & M_PM_ENABLE)) { > + if ((cpu_address_mode(env) == PRV_M) && (env->mmte & M_PM_ENABLE)) { > env->cur_pmbase = val; > } > env->mmte |= EXT_STATUS_DIRTY; > @@ -3747,8 +3754,11 @@ static RISCVException write_spmbase(CPURISCVState *env, int csrno, > return RISCV_EXCP_NONE; > } > env->spmbase = val; > - if ((env->priv == PRV_S) && (env->mmte & S_PM_ENABLE)) { > + if ((cpu_address_mode(env) == PRV_S) && (env->mmte & S_PM_ENABLE)) { > env->cur_pmbase = val; > + if (cpu_get_xl(env, PRV_S) == MXL_RV32) { > + env->cur_pmbase &= UINT32_MAX; > + } > } > env->mmte |= EXT_STATUS_DIRTY; > > @@ -3775,8 +3785,11 @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno, > return RISCV_EXCP_NONE; > } > env->upmbase = val; > - if ((env->priv == PRV_U) && (env->mmte & U_PM_ENABLE)) { > + if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) { > env->cur_pmbase = val; > + if (cpu_get_xl(env, PRV_U) == MXL_RV32) { > + env->cur_pmbase &= UINT32_MAX; > + } > } > env->mmte |= EXT_STATUS_DIRTY; > ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 0/2] target/riscv: Fix the xlen for data address when MPRV=1 2023-06-14 3:25 [PATCH 0/2] target/riscv: Fix the xlen for data address when MPRV=1 Weiwei Li 2023-06-14 3:25 ` [PATCH 1/2] target/riscv: Add additional xlen for " Weiwei Li 2023-06-14 3:25 ` [PATCH 2/2] target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV Weiwei Li @ 2023-06-23 2:22 ` Alistair Francis 2 siblings, 0 replies; 6+ messages in thread From: Alistair Francis @ 2023-06-23 2:22 UTC (permalink / raw) To: Weiwei Li Cc: qemu-riscv, qemu-devel, palmer, alistair.francis, bin.meng, dbarboza, zhiwei_liu, wangjunqiang, lazyparser On Wed, Jun 14, 2023 at 1:27 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > Currently, we use the current env->xl as the xlen for address. However, the xlen for data address should be changed to the xlen related to MPP when MPRV=1. > > The port is available here: > https://github.com/plctlab/plct-qemu/tree/plct-addr-xl-upstream > > Weiwei Li (2): > target/riscv: Add additional xlen for address when MPRV=1 > target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV Thanks! Applied to riscv-to-apply.next Alistair > > target/riscv/cpu.h | 49 +++++++++++++++++++++++++++++++++------ > target/riscv/cpu_helper.c | 8 +++++-- > target/riscv/csr.c | 27 +++++++++++++++------ > target/riscv/translate.c | 13 ++++++++++- > 4 files changed, 80 insertions(+), 17 deletions(-) > > -- > 2.25.1 > > ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-06-23 2:23 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-06-14 3:25 [PATCH 0/2] target/riscv: Fix the xlen for data address when MPRV=1 Weiwei Li 2023-06-14 3:25 ` [PATCH 1/2] target/riscv: Add additional xlen for " Weiwei Li 2023-06-14 9:18 ` Daniel Henrique Barboza 2023-06-14 3:25 ` [PATCH 2/2] target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV Weiwei Li 2023-06-14 9:18 ` Daniel Henrique Barboza 2023-06-23 2:22 ` [PATCH 0/2] target/riscv: Fix the xlen for data address when MPRV=1 Alistair Francis
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